Rabbit 4000 Microprocessor User's Manual

A - B - C - D - E - F - G - H - I - J - K - L - M - N - O - P - Q - R - S - T - U - V - W - X - Y - Z

Index

Numerics

32 kHz clock 1

oscillator circuit 1

B

block diagram

bootstrap 1

breakpoints 1

clocks 1

DMA channels 1

external I/O control 1

external interrupts 1

input capture channels 1

memory management 1

Network Port A 1

Parallel Port A 1

Parallel Port B 1

Parallel Port C 1

Parallel Port D 1

Parallel Port E 1

PWM 1

quadrature decoder 1

Rabbit 4000 1

reset 1

Serial Ports A – D 1

Serial Ports E – F 1

slave port 1

system management 1

Timer A 1

Timer B 1

Timer C 1

bootstrap 1

block diagram 1

dependencies 1

memory fetch 1

onchip-encryption SRAM 1

register descriptions 1

registers 1

breakpoints 1

block diagram 1

dependencies 1

interrupts 1

example ISR 1

memory vs. I/O accesses 1

operation 1

overview 1

register descriptions 1

registers 1

bugs

workarounds 1

DMA requests to internal
I/O registers 1, 2

DMA/block copy interaction 1, 2

DMA/HDLC/Ethernet interaction 1, 2

stack protection/DMA interaction 1, 2, 3

C

clock modes 1

clocks 1

32 kHz clock 1

oscillator circuit 1

power consumption 1

block diagram 1

clock doubler 1, 2

clock modes 1

clock speeds 1

doubling/dividing 1

EMI mitigation 1

Ethernet clock 1

maximum clock speed 1

operation 1

overview 1

power consumption 1

register descriptions 1

registers 1

sleepy clock modes 1

spectrum spreader 1, 2

comparison with other Rabbit microprocessors 1

D

design considerations

BGA package 1

design guidelines

ESD 1

dimensions

BGA package 1

LQFP package 1

DMA channels 1

block diagram 1

buffer descriptor 1

buffer descriptor modes 1

channel priorities 1

clocks 1

control 1

dependencies 1

DMA/block copy interaction 1, 2

external requests 1

interrupts 1, 2, 3

example ISR 1

memory addresses 1

operation 1

overview 1

priorities 1

register descriptions 1

registers 1

setup 1

single-byte DMA requests
to internal I/O registers
1, 2

timed requests 1

transfer 1, 2

transfer priorities 1

transfer priority 1

transfer rates 1

transfers 1

use with peripherals 1

DMA/HDLC/Ethernet interaction 1, 2

Ethernet 1

HDLC serial ports 1

PWM and Timer C 1

DMA control 1

E

ESD

design guidelines 1

ESD sensitivity 1, 2

Ethernet interface circuit 1

Ethernet.

See Network Port A1

external I/O bus 1

operation 1

handshake 1

strobes 1

external I/O control 1

block diagram 1

clocks 1

dependencies 1

external I/O bus 1

handshake 1

operation 1

external I/O bus 1

handshake 1

strobes 1

overview 1

register descriptions 1

registers 1

strobes 1

H

hardware debugging.

See breakpoints1

I

input capture channels 1

block diagram 1

clocks 1

dependencies 1

interrupts 1, 2

example ISR 1

load parallel port output registers 1

measure pulse widths 1

modes 1

input-capture mode 1

input-count mode 1

operation 1

input-capture mode 1

input-count mode 1

overview 1

register descriptions 1

registers 1

start and stop events 1

interrupt priorities 1

interrupts 1

breakpoints 1

example ISR 1

DMA channels 1, 2, 3

example ISR 1

external interrupt vector table
1

external interrupts 1, 2

block diagram 1

clocks 1

dependencies 1

example ISR 1

interrupt vectors 1

operation 1

register descriptions 1

registers 1

input capture channels 1, 2

example ISR 1

internal interrupt vector table
1

interrupt priorities 1

memory management 1

Network Port A 1, 2

operation 1

Parallel Port D 1

Parallel Port E 1

priority levels 1

PWM 1, 2, 3

example ISR 1

quadrature decoder 1, 2

example ISR 1

Serial Ports A – D 1

Serial Ports E – F 1

slave port 1, 2, 3

example ISR 1

system management 1, 2, 3

System/User mode 1, 2

Timer A 1, 2

example ISR 1

Timer B 1, 2

example ISR 1

Timer C 1, 2

example ISR 1

L

land pattern

BGA package 1

LQFP package 1

low-power operation 1

clock rates 1

clock modes 1

current draw for ultra sleepy modes 1

current draw vs. clock frequency 1

handling unused pins 1

operation 1

overview 1

register descriptions 1

registers 1

self-timed chip selects 1

short chip selects 1

LQFP package

mechanical dimensions 1

M

memory

read and write cycles (no wait states) 1

memory management 1

block diagram 1

clocks 1

dependencies 1

interrupts 1

logical memory space 1

mapping physical memory space 1

MMU operation 1

operation 1

16-bit and page modes 1

8-bit operation 1

advanced memory modes
1

instruction and data space
1

memory protection 1

MMU 1

read and write transactions
1

stack protection 1

stack protection/DMA interaction 1, 2

overview 1

physical and logical memory mapping 1

register descriptions 1

registers 1, 2, 3

memory protection 1

N

Network Port A 1

block diagram 1

clock 1

clocks 1

dependencies 1

DMA transfers 1

Ethernet interface circuit 1

high-level protocols 1

interrupts 1, 2

operation 1

multicast addressing 1

receive 1

transmit 1

overview 1

receiver 1

register descriptions 1

registers 1

setup 1

transmitter 1

O

onchip Ethernet.

See Network Port A1

opcodes

System/User mode 1

P

Parallel Port A 1

alternate output functions 1

block diagram 1

clocks 1

external I/O data bus 1

operation 1

overview 1

register description 1

register descriptions 1

registers 1

slave port data bus 1

Parallel Port B 1

alternate output functions 1

block diagram 1

clocks 1

dependencies 1

external I/O bus 1

operation 1

overview 1

register descriptions 1

registers 1

slave port enabled 1

SPCR setup 1

Parallel Port C 1

alternate input functions 1

alternate output functions 1

block diagram 1

clocks 1

dependencies 1

operation 1

overview 1

PCDR setup 1

default 1

register descriptions 1

registers 1

Parallel Port D 1

alternate input functions 1

alternate output functions 1

block diagram 1

clocks 1

dependencies 1

interrupts 1

operation 1

overview 1

PDDR setup 1

register descriptions 1

registers 1

Parallel Port E 1

alternate input functions 1

alternate output functions 1

block diagram 1

clocks 1

dependencies 1

interrupts 1

operation 1

overview 1

PEDR setup 1

register descriptions 1

registers 1

peripherals

system management 1

pin descriptions 1

alternate pin functions

Parallel Port A and B outputs 1

Parallel Port C, D, and E outputs 1

parallel port inputs 1

pin functions 1

alternate pin functions

Parallel Port A and B outputs 1

Parallel Port C, D, and E outputs 1

parallel port inputs 1

pinout 1

BGA package 1

LQFP package 1

power consumption 1

pulse width modulator.

See PWM1

PWM 1

block diagram 1

channels 1

clocks 1

dependencies 1

DMA channels 1

interrupts 1, 2, 3

example ISR 1

operation 1

outputs 1, 2

overview 1

register descriptions 1

registers 1

spreading function 1

Q

quadrature decoder 1

block diagram 1

clocks 1, 2

counter operation 1

dependencies 1

inputs 1

interrupts 1, 2, 3

example ISR 1

operation 1

overview 1

register descriptions 1

registers 1

R

Rabbit 2000 1

Rabbit 3000 1

Rabbit 4000 1

block diagram 1

comparison with other Rabbit microprocessors 1

feature summary 1

features 1

10Base-T Ethernet 1

DMA access 1

EMI mitigation 1

input-capture channels 1

instruction set 1

memory access 1

onchip-encryption RAM 1

parallel ports 1

protected operating systems
1

PWM outputs 1

quadrature-decoder channels 1

timers 1

revision history 1

specifications 1

Rabbit Semiconductor

history 1

registers

alphabetic listing

ACSxCR 1

BDCR 1

BxA0R 1

BxA1R 1

BxA2R 1

BxCR 1

BxM0R 1

BxM1R 1

BxM2R 1

DATASEG 1

DATASEGH 1

DATASEGL 1

DMALR 1

DMCR 1

DMCSR 1

DMHR 1

DMR0CR 1

DMR1CR 1

DMTCR 1

DTRCR 1

DTRDHR 1

DTRDLR 1

DxBCR 1

DxBU0R 1

DxBU1R 1

DxDA0R 1

DxDA1R 1

DxDA2R 1

DxIA0R 1

DxIA1R 1

DxIA2R 1

DxL0R 1

DxL1R 1

DxLA0R 1

DxLA1R 1

DxLA2R 1

DxSA0R 1

DxSA1R 1

DxSA2R 1

DxSMR 1

DxTBR 1

DxTMR 1

DyCR 1

EDMR 1

GCDR 1, 2

GCM0R 1

GCM1R 1

GCPU 1

GCSR 1, 2, 3, 4, 5, 6

GOCR 1, 2

GPSCR 1

GREV 1

IBUER 1

ICCR 1

ICCSR 1

ICLxR 1

ICMxR 1

ICSxR 1

ICTxR 1

ICUER 1

IHCR 1

IHSR 1

IHTR 1

IOxCR 1

IUER 1

IxCR 1

MACR 1

MBxCR 1

MECR 1

MMIDR 1

MTCR 1

NAAER 1

NAC0R 1

NAC1R 1

NACDR 1

NACER 1

NACR 1, 2

NACSR 1

NADR 1

NALDR 1

NAMFR 1

NAMFxR 1

NAMHR 1

NAPAxR 1

NAPCR (network port disabled) 1

NAPCR (network port enabled) 1

NARCR 1

NARR 1

NARSR 1

NASR 1

NATCR 1

NATSR 1

PADR 1

PAUER 1

PBDDR 1

PBDR 1

PBUER 1

PCAHR 1, 2

PCALR 1, 2

PCDCR 1

PCDDR 1

PCDR 1

PCFR 1, 2

PCUER 1

PDAHR 1, 2

PDALR 1, 2

PDB0R 1

PDB1R 1

PDB2R 1

PDB3R 1

PDB4R 1

PDB5R 1

PDB6R 1

PDB7R 1

PDCR 1

PDDCR 1

PDDDR 1

PDDR 1

PDFR 1, 2

PDUER 1

PEAHR 1, 2

PEALR 1, 2

PEB0R 1

PEB1R 1

PEB2R 1

PEB3R 1

PEB4R 1

PEB5R 1

PEB6R 1

PEB7R 1

PECR 1

PEDCR 1

PEDDR 1

PEDR 1

PEFR 1, 2

PEUER 1

PWBAR 1

PWBPR 1

PWL0R 1

PWL1R 1

PWLxR 1

PWMxR 1

PWUER 1

QDCR 1

QDCSR 1

QDCxHR 1

QDCxR 1

QDUER 1

RAMSR 1

RTCCR 1

RTCxR 1

RTUER 1

SAUER 1

SBUER 1

SCUER 1

SDUER 1

SEGSIZ 1

SEUER 1

SFUER 1

SPCR 1, 2, 3, 4, 5

SPDxR 1

SPSR 1

SPUER 1

STKCR 1

STKHLR 1

STKLLR 1

STKSEG 1

STKSEGH 1

STKSEGL 1

SWDTR 1

SxAR 1, 2

SxCR 1

SxCr 1

SxDHR 1, 2

SxDLR 1, 2

SxDR 1, 2

SxER (asynch mode)
1, 2

SxER (clocked serial mode)
1

SxER (HDLC mode) 1

SxLR 1, 2

SxSR (asynch mode)
1, 2

SxSR (clocked serial mode)
1

SxSR (HDLC mode) 1

TACR 1

TACSR 1

TAPR 1

TATxR 1

TAUER 1

TBCLR 1

TBCMR 1

TBCR 1

TBCSR 1

TBLxR 1

TBMxR 1

TBSLxR 1

TBSMxR 1

TBUER 1

TCBAR 1

TCBPR 1

TCCR 1

TCCSR 1

TCDHR 1

TCDLR 1

TCRxHR 1

TCRxLR 1

TCSxHR 1

TCSxLR 1

TCUER 1

VRAM00–VRAM1F 1

WDTCR 1

WDTTR 1

WPCR 1

WPSxHR 1

WPSxLR 1

WPSxR 1

WPxR 1

bootstrap 1

breakpoints 1

Breakpoint x Address 0 Register 1

Breakpoint x Address 1 Register 1

Breakpoint x Address 2 Register 1

Breakpoint x Control Register 1

Breakpoint x Mask 0 Register 1

Breakpoint x Mask 1 Register 1

Breakpoint x Mask 2 Register 1

Breakpoint/Debug Control Register 1

clocks 1

Global Clock Double Register 1

Global Clock Modulator 0 Register 1

Global Clock Modulator 1 Register 1

Global Control/Status Register 1

Global Output Control Register 1

Network Port A Control Register 1

DMA channels 1

DMA Master Auto-Load Register 1

DMA Master Control Register 1

DMA Master Control/Status Register 1

DMA Master Halt Register
1

DMA Master Request 0 Control Register 1

DMA Master Request 1 Control Register 1

DMA Master Timing Control Register 1

DMA Source Addr[7:0] Register 1

DMA Timed Request Control Register 1

DMA Timed Request Divider High Register 1

DMA Timed Request Divider Low Register 1

DMA x Buffer Complete Register 1

DMA x Buffer Unused[15:8] Register 1

DMA x Buffer Unused[7:0] Register 1

DMA x Control Register 1

DMA x Destination Addr[15:8] Register 1

DMA x Destination Addr[23:16] Register 1

DMA x Destination Addr[7:0] Register 1

DMA x Initial Addr[15:8] Register 1

DMA x Initial Addr[23:16] Register 1

DMA x Initial Addr[7:0] Register 1

DMA x Length[15:8] Register 1

DMA x Length[7:0] Register 1

DMA x Link Addr[15:8] Register 1

DMA x Link Addr[23:16] Register 1

DMA x Link Addr[7:0] Register 1

DMA x Source Addr[15:8] Register 1

DMA x Source Addr[23:16] Register 1

DMA x State Machine Register 1

DMA x Termination Byte Register 1

DMA x Termination Mask Register 1

external I/O control 1

I/O Bank x Control Register
1

I/O Handshake Control Register 1

I/O Handshake Select Register 1

I/O Handshake Timeout Register 1

Parallel Port C Alternate High Register 1

Parallel Port C Alternate Low Register 1

Parallel Port C Function Register 1

Parallel Port D Alternate High Register 1

Parallel Port D Alternate Low Register 1

Parallel Port D Function Register 1

Parallel Port E Alternate High Register 1

Parallel Port E Alternate Low Register 1

Parallel Port E Function Register 1

Slave Port Control Register
1

external interrupts 1

Interrupt x Control Register
1

input capture channels 1

Input Capture Control Register 1

Input Capture Control/Status Register 1

Input Capture LSB x Register 1

Input Capture MSB x Register 1

Input Capture Source x Register 1

Input Capture Trigger x Register 1

low-power operation 1

Global Clock Double Register 1

Global Control/Status Register 1

Global Power Save Control Register 1

memory management 1, 2

Advanced Chip Select x Control Register 1

Data Segment High Register
1

Data Segment Low Register
1

Data Segment Register 1

Memory Alternate Control Register 1

Memory Bank x Control Register 1

Memory Timing Control Register 1

MMU Expanded Code Register 1

MMU Instruction/Data Register 1

RAM Segment Register 1

Segment Size Register 1

Stack High Limit Register 1

Stack Limit Control Register 1

Stack Low Limit Register 1

Stack Segment High Register 1

Stack Segment Low Register 1

Stack Segment Register 1

Write Protect Segment x High Register 1

Write Protect Segment x Low Register 1

Write Protect Segment x Register 1

Write Protect x Register 1

Write Protection Control Register 1

Network Port A 1

Network Port A Alignment Error Register 1

Network Port A Checksum 0 Register 1

Network Port A Checksum 1 Register 1

Network Port A Collision Detect Register 1

Network Port A Control Register 1

Network Port A Control/Status Register 1

Network Port A CRC Error Register 1

Network Port A Data Register 1

Network Port A Last Data Register 1

Network Port A Missed Frame Register 1

Network Port A Multicast Filter x Register 1

Network Port A Multicast Hash Register 1

Network Port A Physical Address x Register 1

Network Port A Pin Control Register (network port disabled) 1

Network Port A Pin Control Register (network port enabled) 1

Network Port A Receive Control Register 1

Network Port A Receive Status Register 1

Network Port A Reset Register 1

Network Port A Status Register 1

Network Port A Transmit Control Register 1

Network Port A Transmit Status Register 1

Parallel Port A 1

Parallel Port A Data Register 1

Slave Port Control Register
1

Parallel Port B 1

Parallel Port B Data Direction Register 1

Parallel Port B Data Register 1

Slave Port Control Register
1

Parallel Port C 1

Parallel Port C Alternate High Register 1

Parallel Port C Alternate Low Register 1

Parallel Port C Data Direction Register 1

Parallel Port C Data Register 1

Parallel Port C Drive Control Register 1

Parallel Port C Function Register 1

Parallel Port D 1

Parallel Port D Alternate High Register 1

Parallel Port D Alternate Low Register 1

Parallel Port D Bit 0 Register 1

Parallel Port D Bit 1 Register 1

Parallel Port D Bit 2 Register 1

Parallel Port D Bit 3 Register 1

Parallel Port D Bit 4 Register 1

Parallel Port D Bit 5 Register 1

Parallel Port D Bit 6 Register 1

Parallel Port D Bit 7 Register 1

Parallel Port D Control Register 1

Parallel Port D Data Direction Register 1

Parallel Port D Data Register 1

Parallel Port D Drive Control Register 1

Parallel Port D Function Register 1

Parallel Port E 1

Parallel Port E Alternate High Register 1

Parallel Port E Alternate Low Register 1

Parallel Port E Bit 0 Register 1

Parallel Port E Bit 1 Register 1

Parallel Port E Bit 2 Register 1

Parallel Port E Bit 3 Register 1

Parallel Port E Bit 4 Register 1

Parallel Port E Bit 5 Register 1

Parallel Port E Bit 6 Register 1

Parallel Port E Bit 7 Register 1

Parallel Port E Control Register 1

Parallel Port E Data Direction Register 1

Parallel Port E Data Register 1

Parallel Port E Drive Control Register 1

Parallel Port E Function Register 1

PWM 1

PWM Block Access Register 1

PWM Block Pointer Register 1

PWM LSB 0 Register 1

PWM LSB 1 Register 1

PWM LSB x Register 1

PWM MSB x Register 1

quadrature decoder 1

Quad Decode Control Register 1

Quad Decode Control/Status Register 1

Quad Decode Count High Register 1

Quad Decode Count Register 1

reset 1

reset/bootstrap

Slave Port Control Register
1

Serial Ports A – D 1

Serial Port x Address Register 1

Serial Port x Control Register 1

Serial Port x Data
Register 1

Serial Port x Divider High Register 1

Serial Port x Divider Low Register 1

Serial Port x Extended Register (asynch mode) 1

Serial Port x Extended Register (clocked serial mode)
1

Serial Port x Long Stop Register 1

Serial Port x Status Register (asynch mode) 1

Serial Port x Status Register (clocked serial mode) 1

Serial Ports E – F 1

Serial Port x Address Register 1

Serial Port x Control Register 1

Serial Port x Data
Register 1

Serial Port x Divider High Register 1

Serial Port x Divider Low Register 1

Serial Port x Extended Register (asynch mode) 1

Serial Port x Extended Register (HDLC mode) 1

Serial Port x Long Stop Register 1

Serial Port x Status Register (asynch mode) 1

Serial Port x Status Register (HDLC mode) 1

slave port 1

Slave Port Control Register
1

Slave Port Data x Registers
1

Slave Port Status Register
1

system management 1

Battery-Backed Onchip-Encryption RAM 1

Global Control/Status Register 1

Global CPU Register 1

Global Output Control Register 1

Global Revision Register 1

Real-Time Clock Control Register 1

Real-Time Clock x
Register 1

Secondary Watchdog Timer Register 1

Watchdog Timer Control Register 1

Watchdog Timer Test Register 1

System/User mode 1

Enable Dual-Mode
Register 1

External Interrupt User Enable Register 1

I/O Bank User Enable Register 1

Input Capture User Enable Register 1

Parallel Port A User Enable Register 1

Parallel Port B User Enable Register 1

Parallel Port C User Enable Register 1

Parallel Port D User Enable Register 1

Parallel Port E User Enable Register 1

PWM User Enable
Register 1

Quad Decode User Enable Register 1

Real-Time Clock User Enable Register 1

Serial Port A User Enable Register 1

Serial Port B User Enable Register 1

Serial Port C User Enable Register 1

Serial Port D User Enable Register 1

Serial Port E User Enable Register 1

Serial Port F User Enable Register 1

Slave Port User Enable Register 1

Timer A User Enable Register 1

Timer B User Enable Register 1

Timer C User Enable Register 1

Timer A 1

Global Control/Status Register 1

Timer A Control Register
1

Timer A Control/Status Register 1

Timer A Prescale Register
1

Timer A Time Constant x Register 1

Timer B 1

Global Control/Status Register 1

Timer B Control Register
1

Timer B Control/Status Register 1

Timer B Count LSB Register 1

Timer B Count LSB x Register 1

Timer B Count MSB Register 1

Timer B Count MSB x Register 1

Timer B Step LSB x Register 1

Timer B Step MSB x Register 1

Timer C 1

Global Control/Status Register 1

Timer C Block Access Register 1

Timer C Block Pointer Register 1

Timer C Control Register
1

Timer C Control/Status Register 1

Timer C Divider High Register 1

Timer C Divider Low Register 1

Timer C Reset x High Register 1

Timer C Reset x Low Register 1

Timer C Set x High Register
1

Timer C Set x Low Register
1

reset 1

block diagram 1

dependencies 1

operation 1

register descriptions 1

registers 1

SMODE pin settings 1

revision history 1

S

serial ports

clock synchronization and data encoding 1

Serial Ports A – D 1

block diagram 1

clocks 1

data clocks 1

dependencies 1

interrupts 1

operation 1

asynchronous mode 1

clocked serial mode
1, 2

overview 1

pin use 1

register descriptions 1

registers 1

SPI clock modes 1

SxSR 1

use of clocked Serial Port C
1

use of clocked Serial Port D
1

Serial Ports E – F 1

asynchronous mode 1

block diagram 1

clocks 1

dependencies 1

HDLC data encoding 1

HDLC mode 1

DPLL counter 1

interrupts 1

operation 1

asynchronous mode 1

HDLC mode 1

overview 1

pin use 1

register descriptions 1

registers 1

SxSR 1

slave port 1, 2

addresses 1

block diagram 1

bootstrap processor 1

clocks 1

dependencies 1

interrupts 1, 2, 3

example ISR 1

operation 1

configurations 1

connections 1

master 1

master/slave communication 1

slave 1

slave/master communication 1

overview 1

pin use 1

R/W timing 1

register descriptions 1

registers 1

slave attention 1

timing diagrams 1

sleepy clock modes 1

SMODE pin settings 1

SPCR

Parallel Port A setup 1

specifications 1, 2

AC characteristics 1

BGA package 1

dimensions 1

land pattern 1

pinout 1

clock speeds 1

recommended clock/memory configurations 1

DC characteristics 1

LQFP package 1

dimensions 1

land pattern 1

PC board layout 1

pinout 1

memory access times 1, 2

external I/O reads 1

external I/O writes 1

memory reads 1

memory writes 1

package 1

power and current consumption 1

battery-backed clock 1

sleep modes 1

spectrum spreader 1, 2

stack protection 1

system management 1

block diagram 1

clocks 1

dependencies 1

interrupts 1

onchip-encryption RAM 1

operation

periodic interrupt 1

real-time clock 1

watchdog timer 1

other registers 1

GCPU register 1

GOCR register 1

GREV register 1

periodic interrupt 1

real-time clock 1

register descriptions 1

registers 1

watchdog timers 1

System/User mode 1

dependencies 1

differences between System mode and User mode 1

inaccessible addresses in User mode 1

interrupts 1, 2

opcodes 1

operation 1

complete operating system
1

enabling 1

memory protection 1

mixed operation 1

overview 1

register descriptions 1

registers 1

use

memory protection 1

T

timers

Timer A 1

block diagram 1

capabilities 1

clocks 1

dependencies 1

interrupts 1, 2

example ISR 1

operation 1

overview 1

register descriptions 1

registers 1

reload register operation 1

Timer B 1

block diagram 1

clocks 1

dependencies 1

interrupts 1, 2

example ISR 1

operation 1

overview 1

PWM operation 1

register descriptions 1

registers 1

Timer C 1

block diagram 1

clocks 1

dependencies 1

DMA control 1

interrupts 1, 2

example ISR 1

operation 1

overview 1

register descriptions 1

registers 1

timing diagrams

I/O R/W cycles 1

memory R/W cycles 1

memory R/W cycles (early output enable and write enable) 1

slave port R/W cycles 1, 2

W

watchdog timer

primary watchdog timer 1

primary/secondary watchdog timer bug 1, 2

secondary watchdog timer 1

settings 1