Rabbit 4000 Microprocessor User's Manual

15. Timer C

15.1 Overview

The Timer C peripheral is a 16-bit up-counter clocked by the peripheral clock divided by 2, by the peripheral clock divided by 16, or by the output of countdown timer A1. The counter counts from zero to the limit programmed into the Timer C divider registers and then restarts at zero, so the overall cycle count is the value in the divider registers plus one. There are four Timer C outputs that are called Timers C0–C3. Each output is controlled by a 16-bit set value and a 16-bit reset value. Each output is set to one when the count matches the value in the corresponding set register and is cleared when the count matches the value programmed in the corresponding reset register. This allows the creation of quadrature signals or three-phase signals with a variable frequency for motor-control applications. The values in all of the Timer C registers are transferred to holding registers for use during the count cycle when the counter is reloaded with zeros, allowing the control registers to be reloaded at any time during the count cycle.

Timer C can generate an interrupt when the count limit value is reached.

A separate Timer C Block Access Register (TCBAR) and Timer C Block Pointer Register (TCBPR) are available to allow DMA control of Timer C. The pointer register contains the address of the Timer C register to be accessed via the access register. Each read or write of the access register automatically increments the pointer register through the sequence shown below. Note that only the lower five bits of the pointer actually change. This allows the DMA to write to a fixed internal I/O location but still program all of the relevant Timer registers. The pointer register can be written and read if necessary. Normally the pointer register is initialized to 0x02 (the Timer C Divider Low Register), and the DMA then transfers blocks of 18 bytes to completely reprogram Timer C.

0x502 -> 0x503 -> 0x508 -> 0x509 -> 0x50A -> 0x50B ->
0x50C -> 0x50D -> 0x50E -> 0x50F -> 0x518 -> 0x519 ->
0x51A -> 0x51B -> 0x51C -> 0x51D -> 0x51E -> 0x51F ->

When the DMA destination address is the TCBAR, the DMA request from Timer C is connected automatically to the DMA.

15.1.1 Block Diagram

15.1.2 Registers

Register Name	Mnemonic	I/O Address	R/W	Reset
Timer C Control/Status Register	TCCSR	0x0500	R/W	xxxx0000
Timer C Control Register	TCCR	0x0501	R/W	xx000000
Timer C Divider Low Register	TCDLR	0x0502	R/W	00000000
Timer C Divider High Register	TCDHR	0x0503	R/W	00000000
Timer C Set 0 Low Register	TCS0LR	0x0508	R/W	xxxxxxxx
Timer C Set 0 High Register	TCS0HR	0x0509	R/W	xxxxxxxx
Timer C Reset 0 Low Register	TCR0LR	0x050A	R/W	xxxxxxxx
Timer C Reset 0 High Register	TCR0HR	0x050B	R/W	xxxxxxxx
Timer C Set 1 Low Register	TCS1LR	0x050C	R/W	xxxxxxxx
Timer C Set 1 High Register	TCS1HR	0x050D	R/W	xxxxxxxx
Timer C Reset 1 Low Register	TCR1LR	0x050E	R/W	xxxxxxxx
Timer C Reset 1 High Register	TCR1HR	0x050F	R/W	xxxxxxxx
Timer C Set 2 Low Register	TCS2LR	0x0518	R/W	xxxxxxxx
Timer C Set 2 High Register	TCS2HR	0x0519	R/W	xxxxxxxx
Timer C Reset 2 Low Register	TCR2LR	0x051A	R/W	xxxxxxxx
Timer C Reset 2 High Register	TCR2HR	0x051B	R/W	xxxxxxxx
Timer C Set 3 Low Register	TCS3LR	0x051C	R/W	xxxxxxxx
Timer C Set 3 High Register	TCS3HR	0x051D	R/W	xxxxxxxx
Timer C Reset 3 Low Register	TCR3LR	0x051E	R/W	xxxxxxxx
Timer C Reset 3 High Register	TCR3HR	0x051F	R/W	xxxxxxxx
Timer C Block Access Register	TCBAR	0x00F8	W	xxxxxxxx
Timer C Block Pointer Register	TCBPR	0x00F9	W	00000010

15.2 Dependencies

15.2.1 I/O Pins

The four Timer C outputs can be directed to PC0-PC3, PD0-PD3, or PE0-PE3.

15.2.2 Clocks

The timer in Timer C is a 16-bit up-counter clocked by the peripheral clock divided by 2, by the peripheral clock divided by 16, or by the output of timer A1 as selected in TCCR.

15.2.3 Other Registers

Register	Function
GCSR	Select peripheral clock mode.
PCFR, PCALR PDFR, PDALR PEFR, PEALR	Alternate port output selection

15.2.4 Interrupts

A Timer C interrupt is enabled in TCCR, and will occur whenever the count limit value is reached. The interrupt request is cleared when TCCSR is read.

15.3 Operation

The following steps explain how to set up a Timer C timer.

1. Select perclk/2, perclk/16, or countdown timer A1 in TCCR.

2. Load the desired upper limit for the counter into TCDLR and TCDHR. The overall clock count per Timer C cycle will be the value loaded into the divider registers plus one.

3. Load the desired set and reset values for the Timer C outputs into the set and reset registers (TCSxLR, TCSxHR, TCRxLR, and TCRxHR).

4. If you intend to use DMA control of Timer C, use TCBAR to access the Timer C register pointed to by TCBPR.

5. Enable the desired output pins for Timer C by writing to the appropriate parallel port function and alternate output registers.

6. Enable Timer C by writing a 1 to bit 0 of TCCSR.

15.3.1 Handling Interrupts

The following steps explain how an interrupt is used.

1. Write the vector to the interrupt service routine to the internal interrupt table.

2. Configure TCCR to select the interrupt priority (note that interrupts will be enabled once this value is set).

The interrupt request is cleared by reading from TCCSR.

15.3.2 Example ISR

A sample interrupt handler is shown below.

timerC_isr::
   push af              ; save used registers
   ioi ld a, (TCCSR)    ; clear the interrupt request and get status

   ; handle all interrupts flagged in TCCSR here

   pop af               ; restore used registers
   ipres
   ret

15.4 Register Descriptions

Timer C Control/Status Register (TCCSR) (Address = 0x0500)
Bit(s)	Value	Description
7:2		These bits are always read as zero.
1	0	Timer C divider has not reached its maximum value.
(Read-only)	1	Timer C divider has reached its maximum value. This status bit is cleared by the read of this register, as is the Timer C interrupt.
0	0	The main clock for Timer C (the peripheral clock divided by 2) is disabled.
	1	The main clock for Timer C (the peripheral clock divided by 2) is enabled.

Timer C Control Register (TCCR) (Address = 0x0501)
Bit(s)	Value	Description
7:4		These bits are reserved and should be written with zero.
3:2	00	Timer C clocked by the peripheral clock divided by 2.
	01	Timer C clocked by the output of Timer A1.
	10	Timer C clocked by the peripheral clock divided by 16.
	11	Timer C clocked by the peripheral clock divided by 16.
1:0	00	Timer C interrupts are disabled.
	01	Timer C interrupt uses Interrupt Priority 1.
	10	Timer C interrupt uses Interrupt Priority 2.
	11	Timer C interrupt uses Interrupt Priority 3.

Timer C Divider Low Register (TCDLR) (Address = 0x0502)
Bit(s)	Value	Description
7:0		The eight LSBs of the divider limit value for Timer C are stored.

Timer C Divider High Register (TCDHR) (Address = 0x0503)
Bit(s)	Value	Description
7:0		The eight MSBs of the divider limit value for Timer C are stored.

Timer C Set x Low Register (TCS0LR) (Address = 0x0508) (TCS1LR) (Address = 0x050C) (TCS2LR) (Address = 0x0518) (TCS3LR) (Address = 0x051C)
Bit(s)	Value	Description
7:0		Eight LSBs of the match value to set Timer C Output x.

Timer C Set x High Register (TCS0HR) (Address = 0x0509) (TCS1HR) (Address = 0x050D) (TCS2HR) (Address = 0x0519) (TCS3HR) (Address = 0x051D)
Bit(s)	Value	Description
7:0		Eight MSBs of the match value to set Timer C Output x.

Timer C Reset x Low Register (TCR0LR) (Address = 0x050A) (TCR1LR) (Address = 0x050E) (TCR2LR) (Address = 0x051A) (TCR3LR) (Address = 0x051E)
Bit(s)	Value	Description
7:0		Eight LSBs of the match value to reset Timer C Output x.

Timer C Reset x High Register (TCR0HR) (Address = 0x050B) (TCR1HR) (Address = 0x050F) (TCR2HR) (Address = 0x051B) (TCR3HR) (Address = 0x051F)
Bit(s)	Value	Description
7:0		Eight MSBs of the match value to reset Timer C Output x.

Timer C Block Access Register (TCBAR) (Address = 0x00F8)
Bit(s)	Value	Description
7:0		Access the Timer C register pointed to by TCBPR. TCBPR is automatically updated to the next Timer C register address in the sequence.

Timer C Block Pointer Register (TCBPR) (Address = 0x00F9)
Bit(s)	Value	Description
7:5		These bits always read as 0x0.
4:0		Five least significant bits of the Timer C register address for indirect access.

Global Control/Status Register (GCSR) (Address = 0x0000)
Bit(s)	Value	Description
4:2	000	Processor clock from the main clock, divided by eight. Peripheral clock from the main clock, divided by eight.
	001	Processor clock from the main clock, divided by eight. Peripheral clock from the main clock.
	010	Processor clock from the main clock. Peripheral clock from the main clock.
	011	Processor clock from the main clock, divided by two. Peripheral clock from the main clock, divided by two.
	100	Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
	101	Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The fast clock is disabled.
	110	Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four.
	111	Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six.