Rabbit 4000 Microprocessor User's Manual

14. Timer B

14.1 Overview

The Timer B peripheral consists of a ten-bit free running up-counter, two match registers, and two step registers. Timer B is driven by perclk/2, by perclk/16, or by the output of timer A1. Timer B generates an output pulse whenever the counter reaches the match value. This output pulse can generate an interrupt and will set a status bit in the status register. The processor may then write a new value to the match register. This allows Timer B to be used for pulse-width or pulse-position modulation because the outputs of Timer B can clock the outputs on Parallel Ports D and E.

The compare value comes from either the match register or the value internally generated via the step register. When using the match register, a new match value must be written to the match register after each match condition, LSB first. When using the step register, the hardware automatically calculates the next match value by adding the contents of the step register to the current match value. This allows Timer B matches to be generated at regular periods without calculating the new match value during the interrupt service routine.

14.1.1 Block Diagram

14.1.2 Registers

Register Name	Mnemonic	I/O Address	R/W	Reset
Timer B Control/Status Register	TBCSR	0x00B0	R/W	xxxx0000
Timer B Control Register	TBCR	0x00B1	R/W	xx000000
Timer B MSB 1 Register	TBM1R	0x00B2	R/W	xxxxxxxx
Timer B LSB 1 Register	TBL1R	0x00B3	R/W	xxxxxxxx
Timer B MSB 2 Register	TBM2R	0x00B4	R/W	xxxxxxxx
Timer B LSB 2 Register	TBL2R	0x00B5	R/W	xxxxxxxx
Timer B Step LSB 1 Register	TBSL1R	0x00BA	R/W	xxxxxxxx
Timer B Step MSB 1 Register	TBSM1R	0x00BB	R/W	xxxxxxxx
Timer B Step LSB 2 Register	TBSL2R	0x00BC	R/W	xxxxxxxx
Timer B Step MSB 2 Register	TBSM2R	0x00BD	R/W	xxxxxxxx
Timer B Count MSB Register	TBCMR	0x00BE	R	xxxxxxxx
Timer B Count LSB Register	TBCLR	0x00BF	R	xxxxxxxx

14.2 Dependencies

14.2.1 I/O Pins

The output of Timer B does not come out directly on any of the I/O pins. It can be used to control when the output occurs on Parallel Ports D–E.

14.2.2 Clocks

The timer in Timer B can be clocked by perclk/2, perclk/16, or by countdown timer A1 as selected in TBCR.

14.2.3 Other Registers

Register	Function
GCSR	Select peripheral clock mode.

14.2.4 Interrupts

A Timer B interrupt can be generated whenever the counter equals one of the match registers by enabling the appropriate bit in TBCSR. The interrupt request is cleared when TBCSR is read.

14.3 Operation

The following steps explain how to set up a Timer B countdown timer.

1. Select perclk/2, perclk/16, or countdown timer A1 in TBCR.

2. Use TBCR to select whether countdown timers B1–B2 operate normally with the match registers or whether they use the step registers to calculate match values.

3. Enable Timer B by writing a 1 to bit 0 of TBCSR.

14.3.1 Handling Interrupts

The following steps explain how an interrupt is set up and used.

1. Write the vector to the interrupt service routine to the internal interrupt table.

2. Configure TBCSR to select which match registers will generate an interrupt.

3. Configure TBCR to select the interrupt priority (note that interrupts will be enabled once this value is set; this step should be done last).

The interrupt request is cleared by reading from TBCSR.

14.3.2 Example ISR

A sample interrupt handler is shown below.

timerB_isr::
   push af              ; save used registers
   ioi ld a, (TBCSR)    ; clear the interrupt request and get status

   ; handle all interrupts flagged in TBCSR here

   ; reload match register(s) if necessary

   pop af               ; restore used registers
   ipres
   ret

14.4 Register Descriptions

Timer B Control/Status Register (TBCSR) (Address = 0x00B0)
Bit(s)	Value	Description
7:3		These bits always read as zero.
2:1	0	The corresponding Timer B comparator has not encountered a match condition.
(Read-only)	1	The corresponding Timer B comparator has encountered a match condition. These status bits (but not the interrupt enable bits) are cleared by the read of this register, as is the Timer B interrupt.
2:1	0	The corresponding Timer B interrupt is disabled.
(Write-only)	1	The corresponding Timer B interrupt is enabled.
0	0	The main clock for Timer B (the peripheral clock divided by 2) is disabled.
	1	The main clock for Timer B (the peripheral clock divided by 2) is enabled.

Timer B Control Register (TBCR) (Address = 0x00B1)
Bit(s)	Value	Description
7:6		These bits are reserved and should be written with zero.
5	0	Normal Timer B2 operation using the match registers.
	1	Enable Timer B2 to use the step registers to calculate match values.
4	0	Normal Timer B1 operation, using the match registers.
	1	Enable Timer B1 to use the step registers to calculate match values.
3:2	00	Timer B clocked by main Timer B clock (perclk/2).
	01	Timer B clocked by the output of Timer A1.
	10	Timer B clocked by main Timer B clock divided by 8 (perclk/16).
	11	Timer B clocked by main Timer B clock divided by 8 (perclk/16).
1:0	00	Timer B interrupts are disabled.
	01	Timer B interrupt use Interrupt Priority 1.
	10	Timer B interrupt use Interrupt Priority 2.
	11	Timer B interrupt use Interrupt Priority 3.

Timer B Count MSB x Register (TBM1R) (Address = 0x00B2) (TBM2R) (Address = 0x00B4)
Bit(s)	Value	Description
7:6		Two MSBs of the compare value for the Timer B comparator. This compare value will be loaded into the actual comparator when the current compare detects a match.
5:0		These bits are reserved and should be written with zero.

Timer B Count LSB x Register (TBL1R) (Address = 0x00B3) (TBL2R) (Address = 0x00B5)
Bit(s)	Value	Description
7:0		Eight LSBs of the compare value for the Timer B comparator. This compare value will be loaded into the actual comparator when the current compare detects a match.

Timer B Step LSB x Register (TBSL1R) (Address = 0x00BA) (TBSL2R) (Address = 0x00BC)
Bit(s)	Value	Description
7:0		Eight LSBs of the step size for the Timer B comparator. The new compare value will be loaded into the actual comparator when the current compare detects a match.

Timer B Step MSB x Register (TBSM1R) (Address = 0x00BB) (TBSM2R) (Address = 0x00BD)
Bit(s)	Value	Description
7:2		These bits are ignored but should be written with zeros.
1:0		Two MSBs of the step size for the Timer B comparator. The new compare value will be loaded into the actual comparator when the current compare detects a match.

Timer B Count MSB Register (TBCMR) (Address = 0x00BE)
Bit(s)	Value	Description
7:6	read	The current value of the two MSBs of the Timer B counter are reported.
5:0		These bits are always read as zeros.

Timer B Count LSB Register (TBCLR) (Address = 0x00BF)
Bit(s)	Value	Description
7:0	read	The current value of the eight LSBs of the Timer B counter are reported.

Global Control/Status Register (GCSR) (Address = 0x0000)
Bit(s)	Value	Description
4:2	000	Processor clock from the main clock, divided by eight. Peripheral clock from the main clock, divided by eight.
	001	Processor clock from the main clock, divided by eight. Peripheral clock from the main clock.
	010	Processor clock from the main clock. Peripheral clock from the main clock.
	011	Processor clock from the main clock, divided by two. Peripheral clock from the main clock, divided by two.
	100	Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
	101	Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The fast clock is disabled.
	110	Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four.
	111	Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six.