User's Manual
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| Rabbit 4000 Microprocessor User's Manual |
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20. 10Base-T Ethernet
20.1 Overview
Network Port A implements all of the required digital elements of the 10Base-T standard, and is normally used with two channels of the DMA controller. The receiver provides 32 bytes of buffering, and the transmitter has 16 bytes of buffering. Network Port A connects externally through six dedicated pins. The network port can operate in either half-duplex or full-duplex mode, selected via auto-negotiation.
The network port requires an accurate 20 MHz clock to generate the 10 Mbits/s serial rate of 10Base-T. This clock can come from the main system clock or a dedicated 20 MHz input under program control. The clock for the network port may also be disabled to conserve power. The network port contains synchronization circuitry to allow operation from the 20 MHz reference clock while the main system clock runs independently.
The network port transmitter precedes the transmit data automatically with a preamble and start-frame-delimiter, and appends CRC and the end-frame-delimiter after the last byte. Frame transmission starts automatically once the transmit FIFO is full and any interframe gap time or back-off time has expired. Transmission is aborted if a collision is detected, and is retried up to 16 times using the standard random back-off time algorithm. Detection of a collision causes the transmitter to send a 32-bit "jam" pattern of all ones to guarantee that all receivers in the network recognize the collision. The transmitter uses the 10 most-significant bits of the CRC checker, starting with bit 22 and increasing, to generate the initial seed for the back-off algorithm. Collisions that occur later than one slot time (512 bit times) are reported as late collisions, but are otherwise treated identically to "normal" collisions. If a transmission is not successful after 16 attempts, the transmitter halts and reports the failure via an interrupt. The transmitter guarantees the 9.6 µs inter-frame gap and implements the fair-access algorithm within the inter-frame gap. The transmitter automatically sends link test pulses, even while otherwise disabled, every 16.0 ms. The transmitter contains a jabber timer, which automatically disables the transmitter after 26.2 ms of continuous transmission. This error condition generates an interrupt and must be answered by resetting the network port. The corresponding DMA channel is automatically halted by this error condition and must be restarted after the network port has been reset.
The Rabbit 4000 does not implement the 10Base-T physical layer on-chip, but provides differential transmit data to simplify the external circuitry required to drive the 10Base-T cabling with the required waveform.
The network port receiver uses the received preamble to synchronize to the phase of the incoming frame, and then waits for the start-frame-delimiter. Character assembly begins at this point and each byte is transferred to the receive FIFO. However, no interrupt or DMA request will occur until after the first six bytes of the frame have been received and checked for an address match. The receiver can receive frames independent of the address (promiscuous mode), or it can receive frames with a physical address match, a broadcast address match, or a multicast address match.
Normal DMA transfers of data begin once an address match occurs, and continue until the end-frame-delimiter is recognized or the line goes idle because of a collision. The network receiver calculates the CRC across the entire frame in parallel with character assembly and reports the result when the end-frame-delimiter is recognized. Normally frames with bad CRC are discarded. The receiver also reports misaligned end-frame-delimiters (those that do not occur on byte boundaries).
To help with handling high-level protocols such as TCP/IP, the network port receiver accumulates a 16-bit checksum across the entire received frame except for the first 14 bytes. The first 14 bytes are the destination address field (six bytes), source address field (six bytes), and the frame length field (two bytes), which are not part of the TCP/IP payload. This checksum is initialized to all zeros during the address compare time, and then each pair of bytes is added to the checksum, with the carry from the previous add carried to the following add. The first-received byte adds to the lower byte of the checksum and the second-received byte adds to the upper byte of the checksum. In the case of a frame with an odd length, the second-received byte value is filled with zeros for the 16-bit add. The checksum at the end of the frame is transferred a holding register so that it can be read by software.
The network port implements the NLP receive link integrity test state machine, which requires link integrity pulses to be detected at certain intervals in the absence of other network activity. For this state machine, the
link_test_minvalue is 4.2 ms, and thelink_test_maxvalue is 52.5 ms. Thelink_loss timeconstant is 78.7 ms. If the network receiver enters the NLP Link Test Fail state because of missing link-test pulses, this state machine requires seven successive properly timed link test pulses (or an equal number of FLP bursts) before reporting that the link is again active. The reset state of this state machine is link-inactive. Note that this is a subtle difference relative to the normal 10Base-T receive link-integrity state machine, which requires either link test pulses or carrier sense to make the link active.The network port implements the auto-negotiation algorithm to determine half-duplex or full-duplex operation. In addition to its normal automatic operation, this feature can be disabled or commanded to execute under software control.
The clock for the network port is initially disabled to conserve power, but may be sourced from either a port pin, the system clock (actually the internal peripheral clock), or the system clock divided by two. Since the network port requires a 20.000 MHz clock, the clock should normally be supplied from the port pin. Using the system clock or a derivative to drive the network port precludes the use of the clock modulator.
The network port receiver uses two pins with various options for the behavior. The network port transmitter uses four pins to provide differential signals with wave-shaping capability. See Section 20.4 for more details.
20.1.1 Block Diagram
20.1.2 Registers
20.2 Dependencies
20.2.1 I/O Pins
The network port has six dedicated pins: two input pins (RxD+ and RxD-) and four output pins (TxD+, TxD-, TxDD+, TxDD-). These pins can be used as general-purpose inputs and outputs if the network port is not being used via NAPCR.
The 20 MHz clock will typically be input from PE6.
Pin PE7 can be enabled as a /LNK signal that will be active low whenever the device has an active link, and inactive high at all other times.
Pin PE5 can be enabled as a /ACT signal that will be active low for 0.1 seconds following each packet transmission, and inactive high at all other times.
20.2.2 Clocks
The network port requires a 20 MHz clock input for proper 10Base-T operation. It is expected that this clock is input from pin PE6, but it is also possible to source this clock from the processor clock or the processor clock divided by two, assuming a 20 MHz or a 40 MHz clock is installed.
If the processor clock is used, the clock doubler and dither should be disabled.
20.2.3 Other Registers
PEFR, PEAHR
Selection of /LNK and /ACT signals.
20.2.4 Interrupts
The network interrupt can be generated by an Ethernet frame received correctly, a frame received with error, a frame transmitted correctly, a frame transmitted with error, error counter overflow, jabber detection, or link status change. The events that generate an interrupt can be selected in NACSR.
The network port interrupt vector is in the IIR at offset 0x1E0. It can be set as Priority 1, 2, or 3 by writing to NACSR.
20.3 Operation
High-level support for TCP/IP and other protocols is beyond the scope of this manual, but this section will describe the low-level operation of the 10Base-T Ethernet peripheral.
20.3.1 Setup
The following steps explain how to set up the network port.
- Write the interrupt vector for the interrupt service routine to the external interrupt table.
- Select the desired interrupts and interrupt priority by writing to NACSR.
- Select the desired network port pin configuration by writing to NAPCR.
- Write the device's physical MAC address to the physical address registers (NAPAxR).
- Write to the multicast filter registers (NAMFxR) to generate a multicast filter.
- Enable the network port transmitter by writing to NATCR.
- Enable the network port receiver by writing to NARCR.
20.3.2 Transmit
The following steps explain how to transmit an Ethernet packet.
- Set up a DMA buffer descriptor that will read the packet data from memory and write it to NADR. Write the buffer descriptor's address to the DMA's initial address registers (see Chapter 19 for more information).
- Enable the DMA transfer by auto-loading the buffer.
- The packet transmission will proceed automatically. If any interrupts were enabled for any transmitted packet events, they will occur upon completion (or error).
Note that network interrupts will occur when the data appears in the network peripheral, but DMA interrupts will occur when the DMA transfer is complete.
20.3.3 Receive
The following steps explain how to receive an Ethernet packet.
- Set up a DMA buffer descriptor that will read the packet data from NADR and write it to memory. Write the buffer descriptor's address to the DMA's initial address registers (see Chapter 19 for more information).
- Enable the DMA transfer by auto-loading the buffer.
- The packet transmission will proceed automatically when data comes in. If any interrupts were enabled for any received packet events, they will occur upon completion (or error).
Note that network interrupts will occur when the data appear in the Ethernet peripheral, but DMA interrupts will occur when the DMA transfer is complete.
20.3.4 Handling Interrupts
The network port interrupt is automatically cleared by reading NACSR.
A sample interrupt handler is shown below.
network_isr::
push af
ioi ld a, (NACSR) ; read the interrupt status
push af ; save status byte for later
bit 6,a ; did receive error occur?
jp nz, handle_rx_err
pop af ; recover network status byte
bit 4,a ; did transmit error occur?
jp nz, handle_tx_err
pop af
bit 2,a ; did link change or jabber occur?
ioi ld a, (NASR) ; get current status to check which one
bit 0,a
jp nz, handle_jabber ; did jabber condition occur?
done:
pop af
ipres
ret
handle_rx_err:
ioi ld a, (NARSR) ; get receiver status
; check why error occurred and respond accordingly
ret
handle_tx_err:
ioi ld a, (NATSR) ; get transmitter status
; check why error occurred and respond accordingly
ret
handle_jabber:
ld a, 0x00
ioi ld (NATCR), a ; disable transmitter
ld a, 0x80
ioi ld (NARR), a ; reset transmitter
ld a, 0x80
ioi ld (NATCR), a ; enable transmitter
ret20.3.5 Multicast Addressing
A physical address match requires that the received frame address is a physical address that matches every bit of the programmed receive address. A broadcast address match requires that all 48 bits of the received frame address be "ones." A multicast address match requires the received frame address to be a multicast address (LSB of the address is one) and a match in the multicast address filter. The multicast address filter uses the six most significant bits of the CRC calculated on the receive address as an index into a 64-by-1 bit table written under program control. A one in the corresponding table entry constitutes a multicast address match as far as the network port is concerned. A table of one set of unique multicast addresses corresponding to each filter bit is shown below. The table shows the least significant byte of the multicast address; the remaining five bytes of the address are all zeros for this set of multicast addresses.
20.4 Ethernet Interface Circuit
This is the recommended circuit for the Rabbit 4000 10Base-T Ethernet interface.
The transmit data output pins consist of two pins for each side of the differential signal. The two pins on each side should be connected through a resistor network as shown to provide proper wave shaping of the outgoing signal.
The receive data input for the network port uses two pins, with the exact definition of the two pins under program control (via NAPCR) according to the table below.
20.5 Register Descriptions
Returns the contents of the receive buffer. This register is not normally accessed by the processor, but is accessed by the DMA channels.
Loads the transmit buffer with a data byte for transmission.
Disable transmitter.
Enable transmitter.
DMA request when FIFO is half empty.
DMA request when FIFO is one-fourth empty.
These bits are reserved and should be written with zeros.
Byte of physical address for receive address filtering.
The latest hash value (the upper six bits of the CRC calculation latched at the end of the destination address field) is returned.
These bits are unused and will always read as zero.
The current value of the collision-detect counter is returned. This counter is cleared by a read of this register.
The current value of the alignment-error counter is returned. This counter is cleared by a read of this register.
The current value of the CRC error counter is returned. This counter is cleared by a read of this register.
The LSB of the checksum for the completed frame is returned in this register.
The MSB of the checksum for the completed frame is returned in this register.
The current value of the missed-frame counter is returned. This counter is cleared by a read of this register.
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