Rabbit 4000 Microprocessor User's Manual

21. Input Capture

21.1 Overview

The input capture peripheral consists of two channels, each of which contains a 16-bit counter and edge-detection circuitry. The input capture channels are usually used to determine the time between events. An event is signaled by a rising or falling edge (or optionally by either edge) on one of 12 input pins that can be selected as the input for either of the two channels. The input-capture channels synchronize their inputs to the input-capture clock (from Timer A8), providing a low-pass filter functionality on the inputs, as shown in Section 21.2.4.

Each channel can be used in one of two modes—input capture or input count.

21.1.1 Input-Capture Mode

In the input-capture mode, the channel starts/stops the counter (clocked by Timer A8) according to the signal edges on various parallel port pins, providing the ability to measure pulse widths and time intervals between external events, time-stamp signal changes on a pin, and measure time intervals between a software start and an external event. An interrupt can also be generated when an edge is detected or when a counter rolls over

A 16 bit counter is used to record the time at which the event takes place. The counter is driven by the output of Timer A8 and can be set to count at a rate ranging from the full clock speed (perclk/2) down to 1/256 the clock speed (perclk/512).

Two events are recognized: a start condition and a stop condition. The start condition may be used to start counting and the stop condition to stop counting. However, the counter may also run continuously or run until a stop condition is encountered. The start and stop conditions may also be used to latch the current count at the instant the condition occurs rather than actually start or stop the counter. The same pin may be used to detect the start and stop condition—for example a rising edge could be the start condition and a falling edge could be the stop condition. The start and stop condition can also be input on separate pins.

The input capture channels can be used to measure the width of fast pulses. This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse. In this case the maximum error in the measurement is approximately 2 periods of the clock used to count the counter. If there is sufficient time between events for an interrupt to take place the unit can be set up to capture the counter value on either start or stop conditions (or both) and cause an interrupt each time the count is captured. The counter can also be cleared and started under software control and then have its value captured in response to an input.

The capture counter can be synchronized with Timer B outputs to load parallel port output registers. This makes it possible to generate an output signal precisely synchronized with an input signal. Usually it will be desired to synchronize one of the input capture counters with the Timer B counter. The count offset can be measured by outputting a pulse at a precise time using Timer B to set the output time and capturing the output pulse with an input capture channel. Once the phase relationship is known between the counters it is then possible to output pulses a precise time delay after an input pulse is captured, provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B. The minimum time delay needed is probably less than 10 µs if the software is done carefully and the clock speed is reasonably high.

21.1.2 Input-Count Mode

In the input-count mode the channel simply increments the counter each time the start condition occurs. The count is enabled by the first Timer A8 clock after the mode is selected, and the stop condition is generated when the count matches the value written into the counter MSB and LSB registers. This allows an interrupt to be generated and the counter halted when a particular count is reached. The stop condition will never occur if no value is written into the registers.

21.1.3 Block Diagram

21.1.4 Registers

Register Name	Mnemonic	I/O Address	R/W	Reset
Input Capture Ctrl/Status Register	ICCSR	0x0056	R/W	00000000
Input Capture Control Register	ICCR	0x0057	W	00000000
Input Capture Trigger 1 Register	ICT1R	0x0058	R/W	00000000
Input Capture Source 1 Register	ICS1R	0x0059	R/W	xxxxxxxx
Input Capture LSB 1 Register	ICL1R	0x005A	R	xxxxxxxx
Input Capture MSB 1 Register	ICM1R	0x005B	R	xxxxxxxx
Input Capture Trigger 2 Register	ICT2R	0x005C	R/W	00000000
Input Capture Source 2 Register	ICS2R	0x005D	R/W	xxxxxxxx
Input Capture LSB 2 Register	ICL2R	0x005E	R	xxxxxxxx
Input Capture MSB 2 Register	ICM2R	0x005F	R	xxxxxxxx

21.2 Dependencies

21.2.1 I/O Pins

Each input-capture channel can accept input from one of the following parallel port pins: PC1, PC3, PC5, PC7, PD1, PD3, PD5, PD7, PE1, PE3, PE5, PE7. Use ICTxR to select which input pin to trigger on.

Note that these pins can be used for other peripherals at the same time as the input-capture peripheral. For example, you can use input capture to use measure the pulse width on a serial port input to measure the baud rate.

21.2.2 Clocks

The 16-bit input-capture counters are clocked from the output of Timer A8, and can run at rates from perclk/2 down to perclk/512 by writing the appropriate value to TAT8R.

21.2.3 Other Registers

Register	Function
TAT8R	Time constant for input-capture clock.

21.2.4 Interrupts

Each input capture channel can generate an interrupt whenever a start/stop condition occurs, or when the counter rolls over to zero. The interrupt request is cleared when ICCSR is read.

The input capture interrupt vector is in the IIR at offset 0x1A0. It can be set as Priority 1, 2, or 3.

The input-capture channels synchronize their inputs to the peripheral clock (further divided by Timer A8). Since the inputs are only sampled in synch with the peripheral clock, any faster state faster changes cannot be detected, which is akin to a digital low-pass filter functionality on the inputs. Because of this, there is some delay between the input transition and when an interrupt is requested, as shown below. The status bits in ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR.

21.3 Operation

21.3.1 Input-Capture Channel

The following steps explain how to set up an input-capture channel.

1. Configure Timer A8 via TAT8R to provide the desired input-capture clock.

2. Configure ICTxR to provide the desired start/stop operation and conditions.

3. Configure ICSxR to select the input pins for the start and stop conditions.

4. Configure ICCR to select either the count or the capture mode.

5. Reset the counter by writing to ICCSR.

21.3.2 Handling Interrupts

The following steps explain how an interrupt is used.

1. Write the vector to the interrupt service routine to the internal interrupt table

2. Configure the Input Capture Control/Status Register (ICCSR) to select events that will generate an interrupt.

3. Configure the Input Capture Control Register (ICCR) to select the interrupt priority (note that interrupts will be enabled once this value is set; this step should be done last).

The following actions occur within the interrupt service routine.

• If needed, the current counter value can be read from ICLxR and LCMxR (reading from ICLxR latches the value of ICLxR, so ICLxR should always be read first)

• If the counter is expected to roll over, determine if that is why the interrupt occurred by reading the status bits in ICCSR and adjusting any software counters accordingly

• The interrupt request should be cleared by reading from ICCSR

21.3.3 Example ISR

A sample interrupt handler is shown below.

ic_isr::
   push af
   ioi ld a, (ICCSR)    ; clear the interrupt request and get status

   ; determine which interrupts have occurred
   ; if rollover, perform any necessary software counter adjustments here
   ; read counter values

   pop af
   ipres
   ret

21.3.4 Capture Mode

Pulse Width or Time Between Events

The following steps explain how to measure the pulse width or time between events.

1. Select the same input pin to perform a pulse-width measurement between the start and stop conditions, or select two different input pins to measure time between events on those pins.

2. Set the counter to start on the start condition and stop on the stop condition, latch on the stop condition, and generate an interrupt on the stop condition.

3. In the interrupt handler, read out the counter to determine the pulse width or time interval between the two events.

Time-Stamp External Events

The following steps explain how to time-stamp external events.

1. Set the trigger for the desired event type.

2. Set the counter to run continuously, latch on the start (and/or stop) condition, and generate an interrupt on the start (and/or stop) condition

3. In the interrupt handler, read out the counter as an event timestamp.

Measure Time Interval from a Software Start to an External Event

The following steps explain how to measure the time interval between a software start and the occurrence of an external event.

1. Set up the counter to run continuously, latch on the stop condition, and generate an interrupt on the stop condition.

2. Set up the stop condition for the event of interest.

3. Reset the counter via ICCSR at the software start.

4. In the interrupt handler, read the counter as a time duration.

21.3.5 Count Mode

The following steps explain how to count pulses.

1. Enable the input-count mode by writing to ICCR and setting the counter to run continuously until the stop condition occurs and to latch on the start condition in ICTxR.

2. If an interrupt is desired at a particular count, write that value into the LSB and MSB registers, and enable the stop condition interrupt in ICCSR.

3. Set the start condition to match the signal type to be counted.

4. Reset the counter by writing to ICCSR.

5. Read the counter at any time to get the current count.

6. If a match value is enabled and generates an interrupt, you can re-enable the count mode by clearing the counter via ICCSR and re-enable the mode in ICTxR back to running continuously until the stop condition occurs.

21.4 Register Descriptions

Input Capture Control/Status Register (ICCSR) (Address = 0x0056)
Bit(s)	Value	Description
7	0	The Input Capture 2 Start condition has not occurred.
(Read)	1	The Input Capture 2 Start condition has occurred.
6	0	The Input Capture 2 Stop condition has not occurred.
(Read)	1	The Input Capture 2 Stop condition has occurred.
5	0	The Input Capture 1 Start condition has not occurred.
(Read)	1	The Input Capture 1 Start condition has occurred.
4	0	The Input Capture 1 Stop condition has not occurred.
(Read)	1	The Input Capture 1 Stop condition has occurred.
3	0	The Input Capture 2 counter has not rolled over to all zeros.
(Read)	1	The Input Capture 2 counter has rolled over to all zeros.
2	0	The Input Capture 1 counter has not rolled over to all zeros.
(Read)	1	The Input Capture 1 counter has rolled over to all zeros.
7:2 (Read)		These status bits (but not the interrupt enable bits) are cleared by the read of this register, as is the Input Capture Interrupt.
7:4	0	The corresponding Input Capture interrupt is disabled.
(Write)	1	The corresponding Input Capture interrupt is enabled.
3	0	No effect on Input Capture 2 counter. This bit always reads as zero.
(Write)	1	Reset Input Capture 2 counter to all zeros and clears the rollover latch.
2	0	No effect on Input Capture 1 counter. This bit always reads as zero.
(Write)	1	Reset Input Capture 1 counter to all zeros and clears the rollover latch.
1:0		These bits are reserved and should be written with zeros. These bits will always be read as zeros.

Input Capture Control Register (ICCR) (Address = 0x0057)
Bit(s)	Value	Description
7	0	Input Capture operation for Input Capture 2.
	1	Input Count operation for Input Capture 2.
6	0	Input Capture operation for Input Capture 1.
	1	Input Count operation for Input Capture 1.
5:2		These bits are reserved and should be written with zero.
1:0	00	Input Capture interrupts are disabled.
	01	Input Capture interrupt use Interrupt Priority 1.
	10	Input Capture interrupt use Interrupt Priority 2.
	11	Input Capture interrupt use Interrupt Priority 3.

Input Capture Trigger x Register (ICT1R) (Address = 0x0058) (ICT2R) (Address = 0x005C)
Bit(s)	Value	Description
7:6	00	Disable the counter. Applies even in Counter operation.
	01	The counter runs from the Start condition until the Stop condition.
	10	The counter runs continuously.
	11	The counter runs continuously, until the Stop condition.
5:4	00	Disable the count latching function. In this case, and with Counter operation only, the ICLxR and ICMxR return the programmed match value.
	01	Latch the count on the Stop condition only.
	10	Latch the count on the Start condition only.
	11	Latch the count on either the Start or Stop condition.
3:2	00	Ignore the starting input.
	01	The Start condition is the rising edge of the starting input.
	10	The Start condition is the falling edge of the starting input.
	11	The Start condition is either edge of the starting input.
1:0	00	Ignore the ending input. These two bits are ignored in Counter operation.
	01	The Stop condition is the rising edge of the ending input.
	10	The Stop condition is the falling edge of the ending input.
	11	The Stop condition is either edge of the ending input.

Input Capture Source x Register (ICS1R) (Address = 0x0059) (ICS2R) (Address = 0x005D)
Bit(s)	Value	Description
7:6	00	Parallel Port C used for Start condition input.
	01	Parallel Port D used for Start condition input.
	10	Parallel Port E used for Start condition input.
	11	This bit combination is reserved and should not be used.
5:4	00	Use port bit 1 for Start condition input.
	01	Use port bit 3 for Start condition input.
	10	Use port bit 5 for Start condition input.
	11	Use port bit 7 for Start condition input.
3:2	00	Parallel Port C used for Stop condition input.
	01	Parallel Port D used for Stop condition input.
	10	Parallel Port E used for Stop condition input.
	11	This bit combination is reserved and should not be used.
1:0	00	Use port bit 1 for Stop condition input.
	01	Use port bit 3 for Stop condition input.
	10	Use port bit 5 for Stop condition input.
	11	Use port bit 7 for Stop condition input.

Input Capture LSB x Register (ICL1R) (Address = 0x005A) (ICL2R) (Address = 0x005E)
Bit(s)	Value	Description
7:0	Read	The least significant eight bits of the latched Input Capture count are returned. Reading the LSB of the count latches the MSB of the count to avoid reading stale data. Reading the MSB of the count opens these latches on the MSB of the count. In Counter operation, if no latching condition is specified the value written to this register is returned.
	Write	The eight LSBs of the match value for counter mode are stored.

Input Capture MSB x Register (ICM1R) (Address = 0x005B) (ICM2R) (Address = 0x005F)
Bit(s)	Value	Description
7:0	Read	The most significant eight bits of the latched Input capture count are returned. In Counter operation, if no latching condition is specified the value written to this register is returned.
	Write	The eight MSBs of the match value for counter mode are stored.