Rabbit 4000 Microprocessor User's Manual

18. Slave Port

18.1 Overview

The slave port is a parallel communication port that can be used to communicate with an external master device. The slave port consists of three data input and data output registers, and a status register.

The data input registers are written by the master (the external device) and are read by the processor. The data output registers are written by the processor and are read by the master. Note that the data registers are named from the point of view of the processor. The slave device can only read the data input registers and write to the data output registers. Similarly, the master device can only read the data input registers and write the data output registers. Both devices can read and write to the status register.

The status register contains the interrupt status bits and a status flag corresponding to each data input or data output register to indicate the empty or full status of the data register. Data registers are marked full when written by the source side of the interface, and are marked empty when read by the destination side of the interface.

The hardware interface to the external master consists of an 8-bit bidirectional data bus with a read strobe, write strobe, and chip select. There are two address lines that select one of the three data registers or the status register.

Table 18-1. Slave Port Addresses

Slave Port Address	Slave Port Register
00	Data Register 0
01	Data Register 1
10	Data Register 2
11	Status Register

A slave attention signal is asserted when the processor writes to one of the slave port data registers (SPD0R), and can be deasserted by the master by performing a dummy write to the status register. This signal can be used to interrupt the master to indicate that the master needs to read data from the slave.

The slave port interrupt is asserted when the master writes to SPD0R. The processor clears this interrupt condition by writing to the status register.

The slave port can be used to bootstrap the processor by setting the SMODE pins appropriately. See Chapter 3 for more information on this mode.

18.1.1 Block Diagram

18.1.2 Registers

Register Name	Mnemonic	I/O Address	R/W	Reset
Slave Port Data 0 Register	SPD0R	0x0020	R/W	xxxxxxxx
Slave Port Data 1 Register	SPD1R	0x0021	R/W	xxxxxxxx
Slave Port Data 2 Register	SPD2R	0x0022	R/W	xxxxxxxx
Slave Port Status Register	SPSR	0x0023	R	00000000
Slave Port Control Register	SPCR	0x0024	R/W	0xx00000

18.2 Dependencies

18.2.1 I/O Pins

When the slave port is enabled by writing to SPCR, the following pins are enabled for slave port mode. Note that enabling the slave port mode will override any general-purpose I/O or auxiliary I/O bus settings for these pins; when the slave port is enabled they will perform slave port functionality.

Table 18-2. Slave Port Pin Functionality

Pin(s)	Slave Port Signal	Direction	Functionality
PA0–PA7	SD0–SD7	Bidirectional	Slave data bus
PB7	/SLVATTN	Output	Slave interrupt request (output)
PB6	/SCS	Input	Slave chip select
PB4–PB5	SA0–SA1	Input	Slave address bus
PB3	/SRD	Input	Slave port read strobe
PB2	/SWR	Input	Slave port write strobe
PE7	/SCS	Input	Alternate slave chip select

18.2.2 Clocks

All slave port operations are based on the processor clock.

18.2.3 Interrupts

A slave port interrupt occurs on the slave device whenever the master writes to SPD0R. The /SLVATTN pin is asserted whenever the slave device writes to SPD0R. Either if these conditions is cleared when either the master or slave reads or writes any of the slave port registers.

The slave port interrupt vector is in the IIR at offset 0x080. It can be set as Priority 1, 2, or 3 by writing to SPCR.

18.3 Operation

Figure 18-1 shows a typical slave port connection between a Rabbit processor as the master and two slaves.

Figure 18-1. Master/Slave Port Connections

These connections are summarized in Table 18-3.

Table 18-3. Typical Slave Port Connections

Master		Slave #1		Slave #2
Data Bus	D0–D7	SD0–SD7	PA0–PA7	SD0–SD7	PA0–PA7
Address Bus	A0–A1	SA0–SA1	PB4–PB5	SA0–SA1	PB4–PB5
I/O Read Strobe	/IORD	/SRD	PB3	/SRD	PB3
I/O Write Strobe	/IOWR	/SWR	PB2	/SWR	PB2
Slave #1 Chip Select (I/O strobe I6)	PD6	/SCS	PB6	–	—
Slave #2 Chip Select (I/O strobe I7)	PD7	—	—	/SCS	PB6
External Interrupt 0 (from Slave #1)	PE0	/SLVATTN	PB7	—	—
External Interrupt 1 (from Slave #2)	PE1	—	—	/SLVATTN	PB7

Note that the slave port on the master Rabbit processor is not used; the master uses the data bus to send and receive data to the slave port data registers on the slave devices.

In this setup, pins PD6 and PD7 are set up as I/O strobe chip selects for the two slave devices, and PE0 and PE1 are used as external interrupt inputs to monitor the /SLVATTN signals from the slaves.

In this setup, the slave port is used as follows:

• The slave responds to the interrupt and reads the slave port data registers.

• When the slave wishes to send data to the master, it writes the slave port data registers, writing SPD0R last, which enables the /SLVATTN signal.

• When the master detects the change on /SLVATTN, it reads the slave port data registers.

18.3.1 Master Setup

1. Enable the I/O strobes on PD6 and PD7 by writing to the appropriate Parallel Port D pin and external I/O registers.

2. Enable the external interrupts on PE0 and PE1 by writing to the appropriate external interrupt registers.

18.3.2 Slave Setup

1. Write the vector to the interrupt service routine to the internal interrupt table.

2. Configure SPCR to select the interrupt priority (note that interrupts will be enabled once this value is set).

18.3.3 Master/Slave Communication

1. The master writes data to the appropriate external I/O address on the data bus for the slave device and register desired. For example, in the setup described here, the master would write to register SPD2R on the first slave by writing to the address 0xC002 (0xC000 for the I6 strobe, and 0x0002 for SPD2R on that slave).

2. If the master is writing multiple bytes, it should write to SPD0R last since that will trigger an interrupt on the slave device. If only one byte is being sent, it should be written to SPD0R.

3. The slave responds to the interrupt, reading the data from the slave port data registers.

18.3.4 Slave/Master Communication

1. The slave writes data to the appropriate slave port data register. If it is writing multiple bytes, SPD0R should be written last, which enables the /SLVATTN line.

2. The master receives an external interrupt from the /SLVATTN line, and reads the data out of the slave port data registers via external I/O reads on the data bus.

18.3.5 Handling Interrupts

The interrupt request on the slave is cleared by either the master or the slave accessing one of the slave port registers. To clear the interrupt without affecting the register values, a dummy write can be made to SPSR.

18.3.6 Example ISR

A sample interrupt handler is shown below.

slave_isr::
   push af             ; save used registers

   ; read the data sent by the master
   ioi ld a, (SPD2R)
   ld (to_slv_d2), a
   ioi ld a, (SPD1R)
   ld (to_slv_d1), a
   ioi ld a, (SPD0R)
   ld (to_slv_d0), a

   ; if a response is required, perform it here
   ld a, (to_mas_d2)
   ioi ld (SPD2R), a
   ld a, (to_mas_d1)
   ioi ld (SPD1R), a

   ld a, (to_mas_d0)
   ioi ld (SPD0R), a   ; this write asserts /SLVATTN

   ; the interrupt request is cleared by any read/write of the registers

   pop af              ; restore used registers
   ipres
   ret

18.3.7 Other Configurations

There are other slave port configurations possible:

• The master could use the auxiliary I/O bus instead of the memory bus.

• All devices could poll the slave port status register to determine when data is present instead of relying on interrupts.

• The master could write to SPD0R, triggering an interrupt on the slave. The slave could then simply write a response into SPD0R, which the master detects by polling SPSR. This configuration is useful when fewer signals are desired, or the master device has no external interrupts available.

If polling is to be used, it is important to note that not all bits in the status register may be updated at once; it is possible to read a transitional value as the register updates. To guarantee a proper polling read, the status register should be read twice; when the same value is read both times the value is correct.

Similarly, it is possible to receive a scrambled value from a data register if it is read while being written. The protocol used should take account of this and prevent it from occurring (the protocol described above guarantees this will not occur).

18.3.8 Timing Diagrams

Figure 18-2 shows the sequence of events when the master reads/writes the slave port registers.

Figure 18-2. Slave Port R/W Timing Diagram

The following table explains the parameters used in Figure 18-2.

Symbol	Parameter	Minimum (ns)	Maximum (ns)
Tsu(SCS)	/SCS Setup Time	5	—
Th(SCS)	/SCS Hold Time	0	—
Tsu(SA)	SA Setup Time	5	—
Th(SA)	SA Hold Time	0	—
Tw(SRD)	/SRD Low Pulse Width	40	—
Ten(SRD)	/SRD to SD Enable Time	0	—
Ta(SRD)	/SRD to SD Access Time	—	30
Tdis(SRD)	/SRD to SD Disable Time	—	15
Tsu(SRW – SRD)	/SWR High to /SRD Low Setup Time	40	—
Tw(SWR)	/SWR Low Pulse Width	40	—
Tsu(SD)	SD Setup Time	10	—
Th(SD)	SD Hold Time	5	—
Tsu(SRD – SWR)	/SRD High to /SWR Low Setup Time	40	—

18.4 Register Descriptions

Slave Port Data x Registers (SPD0R) (Address = 0x0020) (SPD1R) (Address = 0x0021) (SPD2R) (Address = 0x0022)
Bit(s)	Value	Description
7:0	Read	The corresponding byte of the slave port is read.
	Write	The corresponding byte of the slave port is written.

Slave Port Status Register (SPSR) (Address = 0x0023)
Bit(s)	Value	Description
7	0	Processor wrote to SPSR.
	1	Master wrote to Data Register 0.
6	0	Slave port read byte 2 is empty.
	1	Slave port read byte 2 is full.
5	0	Slave port read byte 1 is empty.
	1	Slave port read byte 1 is full.
4	0	Slave port read byte 0 is empty.
	1	Slave port read byte 0 is full.
3	0	Master wrote to SPSR.
	1	Processor wrote to SPD0R.
2	0	Slave port write byte 2 is empty.
	1	Slave port write byte 2 is full.
1	0	Slave port write byte 1 is empty.
	1	Slave port write byte 1 is full.
0	0	Slave port write byte 0 is empty.
	1	Slave port write byte 0 is full.

Slave Port Control Register (SPCR) (Address = 0x0024)
Bit(s)	Value	Description
7	0	Program fetch as a function of the SMODE pins.
	1	Ignore the SMODE pins program fetch function.
6:5	Read	These bits report the state of the SMODE pins.
	Write	These bits are ignored and should be written with zero.
4:2	000	Disable the slave port. Parallel Port A is a byte-wide input port.
	001	Disable the slave port. Parallel Port A is a byte-wide output port.
	010	Enable the slave port, with /SCS from Parallel Port E bit 7.
	011	Enable the auxiliary I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:2] is used for the address bus.
	100	This bit combination is reserved and should not be used.
	101	This bit combination is reserved and should not be used.
	110	Enable the slave port, with /SCS from Parallel Port B bit 6.
	111	Enable the auxiliary I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus.
1:0	00	Slave port interrupts are disabled.
	01	Slave port interrupts use Interrupt Priority 1.
	10	Slave port interrupts use Interrupt Priority 2.
	11	Slave port interrupts use Interrupt Priority 3.