26. Low-Power Operation


Rabbit 4000 Microprocessor User's Manual

26. Low-Power Operation

26.1 Overview

The Rabbit 4000 contains several power-saving features. Since the power consumed by the processor is proportional to the clock speed, the Rabbit 4000 provides 12 clock modes that can go as low as 2 kHz. To further reduce power consumption in those ultra-sleepy modes, various shortened chip select strobes are available to reduce current draw by the attached memory devices.

Figure 26-1 shows a typical current draw as a function of the main clock frequency. The values shown do not include any current consumed by external oscillators or memory. It is assumed that approximately 30 pF is connected to each address line.

Figure 26-1. Typical Current Draw as a Function of the Main Clock Frequency

Figure 26-2 shows a typical current draw for the ultra sleepy modes.

Figure 26-2. Typical Current Draw for the Ultra Sleepy Modes

26.1.1 Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Global Control/Status Register

GCSR

0x0000

R/W

11000000

Global Power Save Control Register

GPSCR

0x000D

R/W

00000000

Global Clock Double Register

GCDR

0x000F

R/W

00000000

26.2 Operation

26.2.1 Unused Pins

Input (or bidirectional) pins that are unused in a design can pick up noise that may cause the transistors in the input buffer to switch states quickly, causing unnecessary current draw. To avoid this, all unused pins should be connected to a weak pullup or pulldown resistor (approximately 100 kohms) and left as inputs. This provides protection from noise when the pin is an input, but also limits the current draw if the pin gets inadvertently enabled as an output.

26.2.2 Clock Rates

The processor and peripheral clocks in the Rabbit 4000 can be run in six different modes using the main oscillator: full speed; divided by 2, 4, 6, or 8; and the processor clock divided by 8 with the peripheral clock at full speed. If the clock doubler is enabled, the options also include twice the main oscillator frequency and the main oscillator divided by 3.

In addition, the 32 kHz clock can be used for the processor and peripheral clocks; the 32 kHz clock can also be divided by 2, 4, 8, or 16, which provides dramatically lower power consumption.

Table 26-1 lists the options for the clock modes and the processor clock frequency.

Table 26-1. Clock Modes

Main Oscillator GCSR Setting

Clock Doubler

32 kHz Divider

Processor Clock
Frequency

Full

On

N/A

2 × Main Oscillator

Full

Off

Main Oscillator

Divided by 2

On

Divided by 2

Off

Main Oscillator / 2

Divided by 4

On

Divided by 6

On

Main Oscillator / 3

Divided by 4

Off

Main Oscillator / 4

Divided by 8

On

Divided by 6

Off

Main Oscillator / 6

Divided by 8

Off

Main Oscillator / 8

Off
(32 kHz divider used)

N/A

Disabled

32.768 kHz

/ 2

16.384 kHz

/ 4

8.192 kHz

/ 8

4.096 kHz

/ 16

2.048 kHz

Depending on the application, the processor can continue executing code normally when the main oscillator is divided down to a lower value. However, when the processor clock is running off of the 32 kHz clock, it is recommended that the Rabbit 4000 be performing a tight polling loop, waiting for a wakeup event.

26.2.3 Short Chip Selects

When running at a reduced clock speed, it is likely that the chip selects for external devices will not need to be active for an entire clock cycle. By reducing the width of the chip select, the power consumption of the memory chip can be reduced without having any affect on the processor itself.

For reduced processor speeds based on the main oscillator, a short chip select can be enabled in GPSCR (this feature is not available when the processor is running at full speed). This feature can be enabled separately for both reads and writes. When enabled, the chip select signals will be the width of two undivided clocks and located at the end of the transaction. The read data in the figures below is sampled by the rising edge of CLKI that terminated the T2 cycle. Wait states are inserted between T1 and T2 so they do not affect the width of the strobe.

When the processor is running off the 32 kHz clock, the short chip select option will produce chip select signal that is the width of a single 32 kHz clock (30.5 microseconds); otherwise the timing is identical to the short chip select options based off the main oscillator. Read strobe figures are shown below.

26.2.4 Self-Timed Chip Selects

Self-timed chip selects can be enabled via GPSCR to reduce power consumption even more when running off the 32kHz oscillator. When self-timed chip selects are enabled, the chip select is only active for a short (selectable) period of time. A sample read and write timing diagram is shown below.

26.3 Register Descriptions

Global Control/Status Register (GCSR) (Address = 0x0000)

Bit(s)

Value

Description

7:6

00

No reset or watchdog timer timeout since the last read.

(rd-only)

01

The watchdog timer timed out. These bits are cleared by a read of this register.

10

This bit combination is not possible.

11

Reset occurred. These bits are cleared by a read of this register.

5

0

No effect on the periodic interrupt. This bit will always be read as zero.

1

Force a periodic interrupt to be pending.

4:2

000

Processor clock from the fast clock, divided by 8.
Peripheral clock from the fast clock, divided by 8.

001

Processor clock from the fast clock, divided by 8.
Peripheral clock from the fats clock.

010

Processor clock from the fast clock.
Peripheral clock from the fast clock.

011

Processor clock from the fast clock, divided by 2.
Peripheral clock from the fast clock, divided by 2.

100

Processor clock from the 32 kHz clock, optionally divided via GPSCR.
Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.

101

Processor clock from the 32 kHz clock, optionally divided via GPSCR.
Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
The fast clock is disabled.

110

Processor clock from the fast clock, divided by 4.
Peripheral clock from the fast clock, divided by 4.

111

Processor clock from the fast clock, divided by 6.
Peripheral clock from the fast clock, divided by 6.

1:0

00

Periodic interrupts are disabled.

01

Periodic interrupts use Interrupt Priority 1.

10

Periodic interrupts use Interrupt Priority 2.

11

Periodic interrupts use Interrupt Priority 3.

Global Power Save Control Register (GPSCR) (Address = 0x000D)

Bit(s)

Value

Description

7:5

000

Self-timed chip selects are disabled.

001

230 ns self-timed chip selects for read and write.

010

170 ns self-timed chip selects for read and write.

011

110 ns self-timed chip selects for read and write.

100

290 ns self-timed chip selects for read only.

101

230 ns self-timed chip selects for read only.

110

170 ns self-timed chip selects for read only.

111

110 ns self-timed chip selects for read only.

4

0

Normal chip select timing for read cycles.

1

Short chip select timing for read cycles (not available in full speed).

3

0

Normal chip select timing for write cycles

1

Short chip select timing for write cycles (not available in full speed).

2:0

000

The 32 kHz clock divider is disabled.

001

This bit combination is reserved and should not be used.

010

This bit combination is reserved and should not be used.

011

This bit combination is reserved and should not be used.

100

32 kHz clock divided by 2 (16.384 kHz).

101

32 kHz clock divided by 4 (8.192 kHz).

110

32 kHz clock divided by 8 (4.096 kHz).

111

32 kHz clock divided by 16 (2.048 kHz).

Global Clock Double Register (GCDR) (Address = 0x000F)

Bit(s)

Value

Description

7:5

These bits are reserved and should be written with zeros.

4:0

00000

The clock doubler circuit is disabled.

00001

6 ns nominal low time.

00010

7 ns nominal low time.

00011

8 ns nominal low time.

00100

9 ns nominal low time.

00101

10 ns nominal low time.

00110

11 ns nominal low time.

00111

12 ns nominal low time.

01000

13 ns nominal low time.

01001

14 ns nominal low time.

01010

15 ns nominal low time.

01011

16 ns nominal low time.

01100

17 ns nominal low time.

01101

18 ns nominal low time.

01110

19 ns nominal low time.

01111

20 ns nominal low time.

10001

3 ns nominal low time.

10010

4 ns nominal low time.

10011

5 ns nominal low time.

other

Any bit combination not listed is reserved and must not be used.

Register Name	Mnemonic	I/O Address	R/W	Reset
Global Control/Status Register	GCSR	0x0000	R/W	11000000
Global Power Save Control Register	GPSCR	0x000D	R/W	00000000
Global Clock Double Register	GCDR	0x000F	R/W	00000000

***Table 26-1. Clock Modes***
Main Oscillator GCSR Setting	Clock Doubler	32 kHz Divider	Processor Clock Frequency
Full	On	N/A	2 × Main Oscillator
Full	Off	Main Oscillator
Divided by 2	On
Divided by 2	Off	Main Oscillator / 2
Divided by 4	On
Divided by 6	On	Main Oscillator / 3
Divided by 4	Off	Main Oscillator / 4
Divided by 8	On
Divided by 6	Off	Main Oscillator / 6
Divided by 8	Off	Main Oscillator / 8
Off (32 kHz divider used)	N/A	Disabled	32.768 kHz
/ 2	16.384 kHz
/ 4	8.192 kHz
/ 8	4.096 kHz
/ 16	2.048 kHz

Global Control/Status Register (GCSR) (Address = 0x0000)
Bit(s)	Value	Description
7:6	00	No reset or watchdog timer timeout since the last read.
(rd-only)	01	The watchdog timer timed out. These bits are cleared by a read of this register.
	10	This bit combination is not possible.
	11	Reset occurred. These bits are cleared by a read of this register.
5	0	No effect on the periodic interrupt. This bit will always be read as zero.
	1	Force a periodic interrupt to be pending.
4:2	000	Processor clock from the fast clock, divided by 8. Peripheral clock from the fast clock, divided by 8.
	001	Processor clock from the fast clock, divided by 8. Peripheral clock from the fats clock.
	010	Processor clock from the fast clock. Peripheral clock from the fast clock.
	011	Processor clock from the fast clock, divided by 2. Peripheral clock from the fast clock, divided by 2.
	100	Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
	101	Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The fast clock is disabled.
	110	Processor clock from the fast clock, divided by 4. Peripheral clock from the fast clock, divided by 4.
	111	Processor clock from the fast clock, divided by 6. Peripheral clock from the fast clock, divided by 6.
1:0	00	Periodic interrupts are disabled.
	01	Periodic interrupts use Interrupt Priority 1.
	10	Periodic interrupts use Interrupt Priority 2.
	11	Periodic interrupts use Interrupt Priority 3.

Global Power Save Control Register (GPSCR) (Address = 0x000D)
Bit(s)	Value	Description
7:5	000	Self-timed chip selects are disabled.
	001	230 ns self-timed chip selects for read and write.
	010	170 ns self-timed chip selects for read and write.
	011	110 ns self-timed chip selects for read and write.
	100	290 ns self-timed chip selects for read only.
	101	230 ns self-timed chip selects for read only.
	110	170 ns self-timed chip selects for read only.
	111	110 ns self-timed chip selects for read only.
4	0	Normal chip select timing for read cycles.
	1	Short chip select timing for read cycles (not available in full speed).
3	0	Normal chip select timing for write cycles
	1	Short chip select timing for write cycles (not available in full speed).
2:0	000	The 32 kHz clock divider is disabled.
	001	This bit combination is reserved and should not be used.
	010	This bit combination is reserved and should not be used.
	011	This bit combination is reserved and should not be used.
	100	32 kHz clock divided by 2 (16.384 kHz).
	101	32 kHz clock divided by 4 (8.192 kHz).
	110	32 kHz clock divided by 8 (4.096 kHz).
	111	32 kHz clock divided by 16 (2.048 kHz).

Global Clock Double Register (GCDR) (Address = 0x000F)
Bit(s)	Value	Description
7:5		These bits are reserved and should be written with zeros.
4:0	00000	The clock doubler circuit is disabled.
	00001	6 ns nominal low time.
	00010	7 ns nominal low time.
	00011	8 ns nominal low time.
	00100	9 ns nominal low time.
	00101	10 ns nominal low time.
	00110	11 ns nominal low time.
	00111	12 ns nominal low time.
	01000	13 ns nominal low time.
	01001	14 ns nominal low time.
	01010	15 ns nominal low time.
	01011	16 ns nominal low time.
	01100	17 ns nominal low time.
	01101	18 ns nominal low time.
	01110	19 ns nominal low time.
	01111	20 ns nominal low time.
	10001	3 ns nominal low time.
	10010	4 ns nominal low time.
	10011	5 ns nominal low time.
	other	Any bit combination not listed is reserved and must not be used.

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