Rabbit 4000 Microprocessor User's Manual

25. Breakpoints

25.1 Overview

The Rabbit 4000 contains seven hardware breakpoints to support debugging. Each hardware breakpoint consists of a 24-bit address match register and a 24-bit mask register. A breakpoint can be generated on an address match for address execution, data read, data write, or any combination thereof. The mask register serves to mask off selected address bits from the address compare. A "one" in a particular bit position in the mask register inhibits the corresponding bit in the address match register from contributing to the address match condition.

When a match occurs, a Level 3 breakpoint interrupt is generated. Note that this means that breakpoints behave differently when the processor is running at Interrupt Priority 3 — the interrupt is generated but will not be handled until the processor drops to a lower priority.

In most cases, a code execution interrupt will be handled at the end of the instruction in which the match occurred. However, because of the time required to perform a 24-bit address match in the processor, a code execution breakpoint that is set on a single-byte, 2-clock instruction will not yet be enabled at the end of that instruction, and the interrupt will instead occur at the end of the next instruction.

Note that a breakpoint may be forced to be pending by setting the corresponding bit in BDCR. This feature allows a breakpoint request to be used as a virtual single-step request by always setting the appropriate bit in the interrupt handler. There is a particular sequence of instructions required to exit properly when the interrupt is left pending.

DMA transfers are treated as normal data reads and writes, although the DMA transfer will complete before the interrupt is taken.

Breakpoints can be enabled for the User Mode, the System Mode, or both.

Another breakpoint feature is the ability to disable the RST 28h instruction. The RST 28h vector was often used as a breakpoint feature by adding that instruction to code; by enabling a bit in BDCR, the RST 28h instruction will execute as a NOP instead, providing an easy way to disable that type of breakpoint.

Note that hardware breakpoints do not differentiate between memory and I/O accesses. Hardware breakpoints are triggered by both memory and by internal I/O reads and writes. This behavior could potentially make it hard to detect a low-memory situation when using breakpoints if internal I/O reads/writes are occurring, but it allows inadvertent I/O accesses to be identified.

25.1.1 Block Diagram

25.1.2 Registers

Register Name	Mnemonic	I/O Address	R/W	Reset
Breakpoint Debug/Control Register	BDCR	0x001C	R/W	00000000
Breakpoint 0 Control Register	B0CR	0x030B	R/W	00000000
Breakpoint 1 Control Register	B1CR	0x031B	R/W	00000000
Breakpoint 2 Control Register	B2CR	0x032B	R/W	00000000
Breakpoint 3 Control Register	B3CR	0x033B	R/W	00000000
Breakpoint 4 Control Register	B4CR	0x034B	R/W	00000000
Breakpoint 5 Control Register	B5CR	0x035B	R/W	00000000
Breakpoint 6 Control Register	B6CR	0x036B	R/W	00000000
Breakpoint 0 Address [0–2] Register	B0AxR	0x030C + x	R/W	00000000
Breakpoint 1 Address [0–2] Register	B1AxR	0x031C + x	R/W	00000000
Breakpoint 2 Address [0–2] Register	B2AxR	0x032C + x	R/W	00000000
Breakpoint 3 Address [0–2] Register	B3AxR	0x033C + x	R/W	00000000
Breakpoint 4 Address [0–2] Register	B4AxR	0x034C + x	R/W	00000000
Breakpoint 5 Address [0–2] Register	B5AxR	0x035C + x	R/W	00000000
Breakpoint 6 Address [0–2] Register	B6AxR	0x036C + x	R/W	00000000
Breakpoint 0 Mask [0–2] Register	B0MxR	0x0308 + x	R/W	00000000
Breakpoint 1 Mask [0–2] Register	B1MxR	0x0318 + x	R/W	00000000
Breakpoint 2 Mask [0–2] Register	B2MxR	0x0328 + x	R/W	00000000
Breakpoint 3 Mask [0–2] Register	B3MxR	0x0338 + x	R/W	00000000
Breakpoint 4 Mask [0–2] Register	B4MxR	0x0348 + x	R/W	00000000
Breakpoint 5 Mask [0–2] Register	B5MxR	0x0358 + x	R/W	00000000
Breakpoint 6 Mask [0–2] Register	B6MxR	0x0368 + x	R/W	00000000

25.2 Dependencies

25.2.1 I/O Pins

There are no I/O pins associated with breakpoints.

25.2.2 Clocks

There are no clocks associated with breakpoints.

25.2.3 Other Registers

There are no other registers associated with breakpoints.

25.2.4 Interrupts

When an enabled address match occurs for a given breakpoint, a breakpoint interrupt occurs. The breakpoint that caused the interrupt must be determined by reading BDCR, which also clears the interrupt. Any of the breakpoint interrupts can be enabled by writing to BDCR.

The breakpoint interrupt vector is in the EIR at offset 0x040. It is always set to Interrupt Priority 3, and is the highest priority interrupt; if two Interrupt Priority 3 vectors are pending, the breakpoint interrupt will always be handled first.

25.3 Operation

The following steps must be taken to enable breakpoints:

1. Write the vector to the interrupt service routine to the external interrupt table.

2. Write the desired breakpoint addresses to the appropriate breakpoint address registers (BxAyR, where x is the breakpoint and y is the byte of the address, 0-2).

3. Write an address mask for the given breakpoints (BxMyR).

4. Select the breakpoint address match type (execute, data read, data write) by writing to the appropriate BxCR.

5. Enable the desired breakpoints by writing to BDCR.

25.3.1 Handling Interrupts

The following actions occur within the interrupt service routine.

• Which breakpoints are pending should be determined by reading BDCR. This also clears the pending breakpoints.

• The desired breakpoint action should be taken.

• If single-step functionality is desired, the breakpoint interrupt should be re-enabled by writing the appropriate bit to BDCR. If this is done, the interrupt handler needs to be exited in a particular manner (see below).

25.3.2 Example ISR

A sample interrupt handler is shown below.

breakpoint_isr::
  push af
  ioi ld a, (BDCR)  ; determine which interrupts are pending and
                    ; clear the interrupt request

  ; handle all breakpoints here

  ; reenable any breakpoints by writing to BDCR

  pop af
  ipres        ; you must exit the handler with these two
  ret          ; instructions if you reenabled breakpoints

25.4 Register Descriptions

Breakpoint/Debug Control Register (BDCR) (Address = 0x001C)
Bit(s)	Value	Description
7	0	Normal RST 28h operation.
	1	RST 28h is NOP.
6:0	0	The corresponding Breakpoint request is not pending.
Read	1	The corresponding Breakpoint request is pending. Reading this register automatically clears all pending breakpoint requests.
6:0	0	No effect on the corresponding Breakpoint request.
Write	1	Make the corresponding Breakpoint request pending.

Breakpoint x Control Register (B0CR) (Address = 0x030B) (B1CR) (Address = 0x031B) (B2CR) (Address = 0x032B) (B3CR) (Address = 0x033B) (B4CR) (Address = 0x034B) (B5CR) (Address = 0x036B) (B6CR) (Address = 0x037B)
Bit(s)	Value	Description
7:6	00	No Breakpoint x on execute address match.
	01	Breakpoint x on User Mode execute address match.
	10	Breakpoint x on System Mode execute address match.
	11	Breakpoint x on System or User Mode execute address match.
5:4	00	No breakpoint x on data read address match.
	01	Breakpoint x on User Mode data read address match.
	10	Breakpoint x on System Mode data read address match.
	11	Breakpoint x on System or User Mode data read address match.
3:2	00	No breakpoint x on write address match.
	01	Breakpoint x on User Mode write address match.
	10	Breakpoint x on System Mode write address match.
	11	Breakpoint x on System or User Mode write address match.
1:0		These bits are reserved and should be written with zeros.

Breakpoint x Address 0 Register (B0A0R) (Address = 0x030C) (B1A0R) (Address = 0x031C) (B2A0R) (Address = 0x032C) (B3A0R) (Address = 0x033C) (B4A0R) (Address = 0x034C) (B5A0R) (Address = 0x036C) (B6A0R) (Address = 0x037C)
Bit(s)	Value	Description
7:0		Breakpoint x Address [7:0].

Breakpoint x Address 1 Register (B0A1R) (Address = 0x030D) (B1A1R) (Address = 0x031D) (B2A1R) (Address = 0x032D) (B3A1R) (Address = 0x033D) (B4A1R) (Address = 0x034D) (B5A1R) (Address = 0x036D) (B6A1R) (Address = 0x037D)
Bit(s)	Value	Description
7:0		Breakpoint x Address [15:8].

Breakpoint x Address 2 Register (B0A2R) (Address = 0x030E) (B1A2R) (Address = 0x031E) (B2A2R) (Address = 0x032E) (B3A2R) (Address = 0x033E) (B4A2R) (Address = 0x034E) (B5A2R) (Address = 0x036E) (B6A2R) (Address = 0x037E)
Bit(s)	Value	Description
7:0		Breakpoint x Address [23:16].

Breakpoint x Mask 0 Register (B0M0R) (Address = 0x0308) (B1M0R) (Address = 0x0318) (B2M0R) (Address = 0x0328) (B3M0R) (Address = 0x0338) (B4M0R) (Address = 0x0348) (B5M0R) (Address = 0x0368) (B6M0R) (Address = 0x0378)
Bit(s)	Value	Description
7:0		Breakpoint x Mask [7:0]. (A one in a bit position inhibits the address compare for that bit position.)

Breakpoint x Mask 1 Register (B0M1R) (Address = 0x0309) (B1M1R) (Address = 0x0319) (B2M1R) (Address = 0x0329) (B3M1R) (Address = 0x0339) (B4M1R) (Address = 0x0349) (B5M1R) (Address = 0x0369) (B6M1R) (Address = 0x0379)
Bit(s)	Value	Description
7:0		Breakpoint x Mask [15:8]. (A one in a bit position inhibits the address compare for that bit position.)

Breakpoint x Mask 2 Register (B0M2R) (Address = 0x030A) (B1M2R) (Address = 0x031A) (B2M2R) (Address = 0x032A) (B3M2R) (Address = 0x033A) (B4M2R) (Address = 0x034A) (B5M2R) (Address = 0x036A) (B6M2R) (Address = 0x037A)
Bit(s)	Value	Description
7:0		Breakpoint x Mask [23:16]. (A one in a bit position inhibits the address compare for that bit position.