Rabbit 4000 Microprocessor User's Manual

29. Package Specifications and Pinout

29.1 LQFP Package

29.1.1 Pinout

Figure 29-1. Package Outline and Pin Assignments

29.1.2 Mechanical Dimensions and Land Pattern

Figure 29-2. Mechanical Dimensions Rabbit LQFP Package

Figure 29-3 shows the PC board land pattern for the Rabbit 4000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pattern Standard, IPC, Northbrook, IL, 1999.

Figure 29-3. PC Board Land Pattern for Rabbit 4000 128-pin LQFP

29.2 Ball Grid Array Package

29.2.1 Pinout

Figure 29-4. Ball Grid Array Pinout Looking Through the Top of Package

29.2.2 Mechanical Dimensions and Land Pattern

Figure 29-5. BGA Package Outline

Table 29-1. Ball and Land Size Dimensions

Nominal Ball Diameter (mm)	Tolerance Variation (mm)	Ball Pitch (mm)	Nominal Land Diameter (mm)	Land Variation (mm)
0.3	0.35–0.25	0.8	0.25	0.25–0.20

The design considerations in Table 29-2 are based on 5 mil design rules and assume a single conductor between solder lands.

Table 29-2. Design Considerations
(all dimensions in mm)

Key	Feature	Recommendation
A	Solder Land Diameter	0.254 (0.010)
B	NSMD Defined Land Diameter	0.406 (0.016)
C	Land to Mask Clearance (min.)	0.050 (0.002)
D	Conductor Width (max.)	0.127 (0.005)
E	Conductor Spacing (typ.)	0.127 (0.005)
F	Via Capture Pad (max.)	0.406 (0.016)
G	Via Drill Size (max.)	0.254 (0.010)

29.3 Rabbit Pin Descriptions

Table 29-3 lists all the pins on the Rabbit 4000 along with the data direction of the pin, its function, and the pin number on the die.

Table 29-3. Rabbit 4000 Pin Descriptions

Pin Group	Pin Name	Direction	Function	LQFP Pin	TFBGA Ball
Hardware	CLK	Output	Internal Clock Output	2	B1
	CLK32K	Input	32 kHz Clock In	48	K6
	/RESET	Input	Master Reset	45	L5
	RESOUT	Output	Reset Output	49	L6
	CLKI	Input	Main Clock In	108	C8
	CLKIEN	Output	Main Clock Enable	109	B8
CPU Buses	A[19:0]	Output	Address Bus	various	various
	D[7:0]	Bidirectional	Data Bus	various	various
Status & Control	/WDTOUT	Output	Watchdog Timer Timeout	41	L4
	STATUS	Output	Instruction Fetch First Byte	4	C1
	SMODE1 SMODE0	Input	Bootstrap Mode & Tamper Detect	42, 43	M4, J5
Chip Selects	/CS0	Output	Memory Chip Select 0	9	D3
	/CS1	Output	Memory Chip Select 1	46	M5
	/CS2	Output	Memory Chip Select 2	3	B2
Output Enables	/OE0	Output	Memory Output Enable 0	5	C2
	/OE1	Output	Memory Output Enable 1	94	D9
Write Enables	/WE0	Output	Memory Write Enable	83	F12
	/WE1	Output	Memory Write Enable	98	B12
I/O Control	/BUFEN	Output	I/O Buffer Enable	40	K4
	/IORD	Output	I/O Read Enable	39	M3
	/IOWR	Output	I/O Write Enable	38	L3
I/O Ports	PA[7:0]	Input/Output	I/O Parallel Port A	99–106	various
	PB[7:0]	Input/Output	I/O Parallel Port B	112–119	various
	PC[7:0]	Input/Output	I/O Parallel Port C	61–73, 66–70	various
	PD[7:0]	Input/Output	I/O Parallel Port D	52–57, 59–60	various
	PE[7:0]	Input/Output	I/O Parallel Port E	28–31, 34–37	various
Network	TXD+ TXD- TXDD+ TXDD-	Output	Network Transmit	124–127	B3 B4 A4 A3
	RXD+ RXD-	Input	Network Receive	121–122	A5 A5