User's Manual
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| Rabbit 4000 Microprocessor User's Manual |
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4. System Management
4.1 Overview
There are a number of basic system peripherals in the Rabbit 4000 processor, some of which are covered in later chapters. The peripherals covered in this chapter are the periodic interrupt, the real-time clock, the watchdog timers, the battery-backed onchip-encryption RAM, and some of the miscellaneous output pins and their control and processor registers that provide the processor ID and revision numbers.
The periodic interrupt, when enabled, is generated every 16 clocks of the 32 kHz clock (every 488 µs, or 2.048 kHz). This interrupt can be used to perform periodic tasks.
The real-time clock (RTC) consists of a 48-bit counter that is clocked by the 32 kHz clock. It is powered by the VBAT pin, and so can be battery-backed. The value in the counter is not affected by reset, and can only be set to zero by writing to the RTC control register. The 48-bit width provides a 272-year span before rollover occurs.
There are two watchdog timers in the Rabbit 4000, both clocked by the 32 kHz clock. The main watchdog timer can be set to time out from 250 ms to 2 seconds, and resets the processor if not reloaded within that time. Its purpose is to restart the processor when it detects that a program gets stuck or disabled.
The secondary watchdog timer can time out from 30.5 µs up to 7.8 ms, and generates a Priority 3 secondary watchdog interrupt when it is not reset within that time. The primary use for the secondary watchdog is to act as a safety net for the periodic interrupt — if the secondary watchdog is reloaded in the periodic interrupt, it will count down to zero if the periodic interrupt stops occurring. In addition, it can be used as a periodic interrupt on its own.
The battery-backed onchip-encryption RAM consists of 32 bytes of memory that are powered by the VBAT pin. Their values are not affected by reset, but are erased if the state of the SMODE pins changes. These 32 bytes are intended for storing sensitive data (such as an encryption key) somewhere other than an external memory device. The "tamper-protection" erase feature prevents loading a program into the onchip-encryption RAM via the programming port and reading out the bytes.
The following other registers are also described in this chapter.
- Global Output Control Register (GOCR), which controls the behavior of the CLK, STATUS, /WDT, and /BUFEN pins
- Global CPU Register (GCPU), which holds the identification number of the processor.
- Global Revision Register (GREV), which hold the revision number of the processor.
4.1.1 Block Diagram
4.1.2 Registers
4.2 Dependencies
4.2.1 I/O Pins
The CLK, STATUS, /WDTOUT, and /BUFEN pins are controlled by GOCR. Each of these pins can be used as general-purpose outputs by driving them high or low:
- the CLK pin can output the peripheral clock, the peripheral clock divided by two, or be driven high or low;
- the STATUS pin can be active low during the first byte of each opcode fetch, active low during an interrupt acknowledge, or driven high or low;
- the /WDTOUT pin can be active low whenever the watchdog timer resets the device or driven low; and
- the /BUFEN pin can be active low during external I/O cycles, active low during data memory cycles, or driven high or low.
The values in the battery-backed onchip-encryption RAM bytes are cleared If the signal on the SMODE pins changes state.
4.2.2 Clocks
The periodic interrupt, real-time clock, watchdog timer, and secondary watchdog timer require the 32 kHz clock.
4.2.3 Interrupts
The periodic interrupt is enabled in GCSR, and will occur every 488 µs. It is cleared by reading GCSR. It can operate at Priority 1, 2, or 3.
The secondary watchdog interrupt will occur whenever the secondary watchdog is enabled and allowed to count down to zero. It is cleared by restarting the secondary watchdog by writing to WDTCR. The secondary watchdog interrupt always occurs at Priority 3.
4.3 Operation
4.3.1 Periodic Interrupt
The following steps explain how a periodic interrupt is used.
- Write the vector to the interrupt service routine to the internal interrupt table.
- Enable the periodic interrupt by writing to GCSR.
- The interrupt request is cleared by reading from GCSR.
A sample interrupt handler is shown below.
periodic_isr::
push af
ioi ld a, (GCSR) ; clear the interrupt request and get status
; handle any periodic tasks here
pop af
ipres
ret4.3.2 Real-Time Clock
The real-time clock consists of six 8-bit registers that together comprise a 48-bit value. The real-time clock is not synchronized to the read operation, so the least-significant bit should be read twice and checked for matching values; if the two reads do not match, then the real-time clock may have been updating during the read and should be read again.
Writing to RTC0R latches the current real-time clock value into the RTCxR holding registers, so the following sequence should be used to read the real-time clock.
- Write any value to RTC0R and then read back a value from RTC0R.
- Write a value to RTC0R again, and again read back a value from RTC0R.
- If the two values do not match, repeat Step 2 until the last two readings are identical.
- At this point, registers RTC1R through RTC6R can also be read and used.
Note that the periodic interrupt and the real-time clock are clocked by the same edge of the 32 kHz clock; if read from the periodic interrupt, the count is guaranteed to be stable and only needs to be read once (assuming it occurs within one clock of the 32 kHz clock).
The real-time clock can be reset by writing the sequence 0x40 – 0x80 to RTCCR. It can be reset and left in the byte increment mode by writing 0x40 – 0xC0 to RTCCR and then writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real-time clock. The byte increment mode is disabled by writing 0x00 to RTCCR.
4.3.3 Watchdog Timer
The watchdog timer is enabled on reset with a 2-second timeout. Unless specific data are written to WDTCR before that time expires, the processor will be reset. The watchdog timer can be disabled by writing a sequence of two bytes to WDTTR as described in the register description.
The watchdog timer also contains a special test mode that speeds up the timeout period by clocking it with the peripheral clock instead of the 32 kHz clock. This mode can be enabled by writing to WDTTR.
4.3.4 Secondary Watchdog Timer
The secondary watchdog timer is disabled on reset, unless the reset occurs because the primary watchdog timer times out while the secondary watchdog timer is enabled. The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling the secondary watchdog on startup or reset by writing 0x5F to WDTCR. The following steps explain how to use the secondary watchdog timer.
- Write the vector to the interrupt service routine to the internal interrupt table.
- Write the desired timeout period to SWDTR. This also enables the secondary watchdog timer.
- Restart the secondary watchdog timer by either writing the timeout period to SWDTR or writing 0x5F to WDTCR.
If the secondary watchdog timer counts down to zero, a Priority 3 secondary watchdog interrupt will occur. This interrupt request is cleared by writing a new timeout value to SWDTR. A sample interrupt handler is shown below.
secwd_isr::
push af
; determine why the interrupt occurred and take appropriate action
ld a, 0x40 ; timeout period of 0x40/32kHz = 1.95ms
ioi ld (SWDTR), a ; clear the interrupt request
pop af
ipres
ret4.4 Register Descriptions
Program fetch as a function of the SMODE pins.
Ignore the SMODE pins program fetch function.
These bits report the state of the SMODE pins.
CPU identifier for this version of the chip.
Program fetch as a function of the SMODE pins.
Ignore the SMODE pins program fetch function.
These bits report the state of the SMODE pins.
Revision identifier for this version of the chip.
General-purpose RAM locations. Cleared by Intrusion Detect conditions.
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