User's Manual
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| Rabbit 4000 Microprocessor User's Manual |
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6. Interrupts
6.1 Overview
The Rabbit 4000 can operate at one of four priority levels, 0–3, with Priority 0 being the expected standard operating level. The current priority and up to three previous priority levels are kept in the processor's 8-bit IP register, where bits 0–1 contain the current priority. Every time an interrupt is handled or an IPSET instruction occurs, the value in the register is shifted left by two bits, and the new priority placed in bits 0–1. When an IPRES or IRET instruction occurs, the value in IP is shifted right by two bits (bits 0–1 are shifted into bits 6–7). On reset, the processor starts at Priority 3.
Most interrupts can be set to be Priority 1–3. A pending interrupt will be handled only if its interrupt priority is greater than the current processor priority. This means that even a Priority 3 interrupt can be blocked if the processor is currently at Priority 3. The System Mode Violation, Stack Limit Violation, Write Protection Violation, secondary watchdog, and breakpoint interrupts are always enabled at Priority 3. In addition, when the system/user mode is enabled and the processor is in the user mode, the processor will not actually enter Priority 3; any attempt to enter Priority 3 will actually be requested as Priority 2.
When an interrupt is handled, a call is executed to a fixed location in the interrupt vector tables; this operation requires 10 clocks, the minimum interrupt latency for the Rabbit 4000. There are two vector tables, the internal and the external interrupt vector tables, that can be located anywhere in logical memory by setting the processor's IIR and EIR registers. The IIR and EIR registers hold the upper byte of each table's address. For example, if IIR is loaded with 0xC4, then the internal interrupt vector table will start at the logical memory address 0xC400.
The internal interrupt vector table occupies 512 bytes, and the external interrupt vector table is 256 bytes in size. Since the RST and SYSCALL vectors use all eight bits of the IIR for addressing, the lowermost bit of IIR should always be set to zero so to keep some vectors from inadvertently overlapping.
Each interrupt's vector begins on a 16-byte boundary inside the vector tables. It may be possible to fit a small routine into that space, but it is typical to place a call to a separate routine in that location.
Some Rabbit 4000 instructions are "chained atomic," which means that an interrupt cannot occur between that instruction and the following instruction. These instructions are useful for doing things like exiting interrupt handlers properly or updating semaphores.
6.2 Operation
To ensure proper operation, all interrupt handler routines should be written according to the following guidelines.
- Push all registers to be used by the routine onto the stack before use, and pop them off the stack before returning from the ISR.
- Keep the ISR as short and fast as possible.
- If the ISR will run for some time, lower the interrupt priority as soon as possible within the ISR to allow other interrupts to occur.
- A number of special rules apply to interrupts when operating in the system/user mode; please see the appropriate chapter for more details.
6.3 Interrupt Tables
Table 6-1 shows the structure of the internal interrupt vector table. The first column is the vector address offset within the table. The second column shows the vectors in the first 256 bytes of the table, and the third column shows the vectors in the second 256 bytes.
Table 6-2 shows the structure of the external interrupt vector table. Each interrupt vector falls on a 16-byte boundary inside the table.
There is a priority among interrupts if multiple requests are pending, as shown in Table 6-3. Interrupts marked as "cleared automatically" have their requests cleared when the interrupt is first handled.
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