Rabbit 2000 Microprocessor User's Manual

15. AC Timing Specifications

The Rabbit 2000 processor may be operated at voltages between 2.5 V and 5.5 V, and at temperatures from -40°C to +85°C with use possible use over the range -55°C to +120°C. Most users will operate the Rabbit at either 5.0 V or 3.3 V. The most computation per watt is obtained at approximately 3.3 V. The highest practical speed is usually obtained at 5 V.

The Rabbit is available in one version, which has a maximum clock speed of 29.4 MHz over the industrial temperature range of -40°C to +85°C. The R30 has a maximum clock speed of 18.9 MHz at 3.3 V ±10%. The maximum clock speed is 11.5 MHz at 2.5 V.

If a half-speed crystal is used with the clock doubler to achieve the desired clock speed, the maximum clock speed must be reduced by 4% to allow for an up to 4% asymmetry (52/48) in the waveform generated by the oscillator. This is because the clock doubler uses the intermediate edge to generate the double frequency. If the clock doubler is used to double 14.7456 MHz to 29.4912 MHz, the operating temperature should be limited to 70°C.

To optimize power consumption, the usual strategy is to use a supply voltage between 3 V and 3.5 V, and the clock speed should be adjusted downward as far as feasible. This will give the maximum computation per watt.

Table 15-1. Rabbit Basic Worst-Case Timings

	2.50 V min. -40°C- +85°C	3.3 V ±10% -40°C- +85°C	3.3V ±5% -40°C- +70°C	5.0 V ±10% -40°C- +85°C	5.0 V ± 5% -40°C- +70°C
Maximum clock speed	11.5 MHz	17.5 MHz	19.25 MHz	29.5 MHz	31.5 MHz
Maximum clock speed generated using clock doubler	11.06 MHz	16.75 MHz	18.5 MHz	28.5 MHz	30.0 MHz
Tadr output delay with 20 pF address line load	15 ns	11 ns	10 ns	8 ns	7 ns
Tadr output delay with 70 pF address line load	27 ns	21 ns	19 ns	15 ns	14 ns
Tsetup	4 ns	4 ns	3 ns	3 ns	2 ns
Toe delay from clock to output enable (10 pF load)	12 ns	8 ns	8 ns	6 ns	5 ns
					2001.01.31

The industrial clock speed values in Table 15-1 (at a maximum temperature of 85°C) are improved by 7% over commercial ratings at 70°C (which are extended to -40°C here). The effect of temperature alone is a clock speed that is approximately 1.2% lower for each 5°C temperature increase. The maximum clock speed is approximately directly proportional to the operating voltage.

If serial communication is to be used at standard baud rates, then certain clock speeds must be used. These clock speeds are usually multiples of 1.8432 MHz to ensure that baud rates of 57,600 bps, 19,200 bps, and less will be available. Multiples of 3.6862 MHz ensure that baud rates of 115,200 bps, 38,400 bps, and less will be available. Multiples of 1.2288 MHz ensure that baud rates of 38,400 bps and less will be available. The standard Rabbit BIOS will accept any clock speed that is a multiple of 0.6144 MHz.

The graphs in Figure 15-1 and Figure 15-2 illustrate the maximum clock speed at which no failure is detected for a typical Rabbit 2000 as the voltage and temperature are varied. The official design specifications specify a lower maximum frequency to allow for process variation.

The die suffers significant self-heating at higher clock speeds. The die to ambient thermal impedance is 44°C/W at zero air flow. At 5 V and a current consumption of 65 mA, this would result in about 15°C of self-heating, and would reduce the maximum clock speed by approximately 3%. This reduction is included in Table 15-2, which provides the memory access time requirements.

When interfacing to memory devices, the memory access time required for a directly interfaced memory is given by:

(1) access time = (clock period)*(2 + wait states) - T_setup - T_adr

where T_adr is the delay between the rising edge of T₁ and address valid, and T_setup is the data setup time relative to the clock. T_adr and T_setup are shown in Figure 15-3 to Figure 15-4 for memory read/write and I/O read/write cycles. Most 5 V memories are TTL compatible in that they switch at 0.8 V and 2.0 V. T_setup is specified from the point at which the input voltage reaches 30% or 70% of VDD for falling and rising signals respectively. T_oe is specified for the time from the clock that is required for the signal to reach 0.8 V.

The T_adr measured was the time required for the signal to fall from a high level to 0.8 V. Tadr depends on the bus loading--address line A0 has a more powerful driver and can handle double the capacitance with the same delay times. The T_adr times also apply to the memory chip select lines.

The formula in Equation (1) remains true if the clock doubler is used, except that the access time must be reduced by 4% of one clock period if there is an odd number of wait states. The length of the T_oe pulse is subjected to a reduction of up to 4% if the clock doubler is used.

Figure 15-1. Rabbit 2000 Typical Maximum Operating Frequency
versus Temperature at 5 V and 3.3 V

Figure 15-2. Rabbit 2000 Typical Maximum Operating Frequency
versus Voltage at 25°C

15.1 Memory Access and I/O Read/Write Times

The memory access time requirements are listed in Table 15-2. It is important that wait states should not be used for any memory that holds code that is being executed. Memory wait states are only intended for use with data accesses. For code memory the clock should be matched to the memory requirements, or one of the clock dividers should be enabled to accommodate slow memory. As a rough guide, each data memory wait state in main RAM that is introduced will reduce the average compute performance by approximately 8%. The data memory read access is slowed by 50% for 1 wait state and is slowed by 100% for 2 wait states. However, since only a small proportion of accesses are data accesses rather than code accesses or instruction fetch cycles, the overall affect on performance is slight. If data memory wait states are introduced, it is important to use the macros specified in the BIOS so that the compiler will be aware of the wait states.

Generally, the maximum operating speed is proportional to the power supply voltage. The operating current is proportional to the voltage, and so the operating power is proportional to the square of the voltage. The operating power is also proportional to the clock speed. Higher temperatures reduce the maximum operating speed by approximately 1% for each 5°C. In addition, higher operating speeds increase the die temperature because of the heat generated and therefore slightly compound the adverse effects of higher temperature.

Table 15-2. Memory Access Time Requirements (V±5%, T -40°C to +70°C)

Clock Speed (MHz)	Period (ns)	Wait States	Memory Access Time @5 V 20 pF Load (ns)	Memory Access Time @5 V 70 pF Load (ns)	Maximum PC- Compatible Baud Rate (bps)
29.4912	34	0	59	52	921,600
27.6480	36.2	0	64	57	57,600
25.8048	38.7	0	69	62	115,200
25.8048	38.7	1	108	101	115,200
25.8048	38.7	2	147	140	115,200
24.576	40.7	0	73	66	38,400
23.9616	41.7	0	75	68	57,600
22.1184	45.2	0	82	75	230,400
22.1184	45.2	1	127	120	230,400
22.1184	45.2	2	173	165	230,400
20.2752	49.3	0	90	83	57,600
18.432	54.2	0	100 @ 5 V 96 @ 3.3 V	93 @ 5 V 87 @ 3.3 V	115,200
14.7456	67.8	0	127 @ 5 V/ 123 @ 3.3 V	120 @ 5 V/ 114 @ 3.3 V	460,800
14.7456	67.8	1	197 @ 5 V/ 193 @ 3.3 V	190 @ 5 V/ 184 @ 3.3 V	460,800
11.0592	90.5	0	172 @ 5 V 168 @ 3.3 V 162 @ 2.5 V(min)	165 @ 5 V/ 159 @ 3.3 V 150 @ 2.5 V(min)	115,200
7.3728	135.6	0	263 @ 5 V/ 259 @ 3.3 V 253 @ 2.5V(min)	256 @ 5 V/ 250 @ 3.3 V/ 241 @ 2.5 V(min)	230,400

Figure 15-3, Figure 15-4, and Figure 15-5 illustrate the memory and I/O read and write cycles. The Rabbit operates at 2 clocks per bus cycle plus any wait states that might be specified.

The following memory read time delays were measured.

Table 15-3. Memory Read Time Delays

Time Delay	Output Capacitance
	20 pF		70 pF
	min.	max.	min.	max.
Clock to address delay (Tadr)	--	8 ns	--	14 ns
Clock to memory chip select delay (TCSx)	--	8 ns	--	14 ns
Clock to memory read strobe delay (TOEx)	--	6 ns	--	12 ns
Data setup time (Tsetup)	3 ns	--	3 ns	--
Data hold time (Thold)	0 ns	--	0 ns	--

The measurements were taken at the 50% points under the following conditions.

• T = -40°C to 85°C, V = 5.0 V ±10%

• Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/4.5 V

The following memory write time delays were measured.

Table 15-4. Memory Write Time Delays

Time Delay	Output Capacitance
	20 pF		70 pF
	min.	max.	min.	max.
Clock to address delay (Tadr)	--	8 ns	--	14 ns
Clock to memory chip select delay (TCSx)	--	8 ns	--	14 ns
Clock to memory write strobe delay (TWEx)	--	6 ns	--	12 ns
High Z to data valid relative to clock (TDHZV)	--	11 ns	--	17 ns
Data valid to high Z relative to clock (TDVHZ)	--	11 ns	--	11 ns

The measurements were taken at the 50% points under the same conditions that the memory read delays were measured.

Figure 15-3. Memory Read and Write Cycles

Notice that the data times are different, depending on whether data are being read or written. T_hold for data read specifies how long the data must remain valid following the rising edge of T1 when the clock cycle repeats. T_DHZV for data write specifies how long the data remain valid once /WEx goes high, and must be at least one-half of a CPU clock cycle.

The following I/O read time delays were measured.

Table 15-5. I/O Read Time Delays

Time Delay	Output Capacitance
	20 pF		70 pF
	min.	max.	min.	max.
Clock to address delay (Tadr)	--	8 ns	--	14 ns
Clock to memory chip select delay (TCSx)	--	8 ns	--	14 ns
Clock to I/O chip select delay (TIOCSx)	--	8 ns	--	14 ns
Clock to I/O read strobe delay (TIORD)	--	6 ns	--	12 ns
Clock to I/O buffer enable delay (TBUFEN)	--	8 ns	--	14 ns
Data setup time (Tsetup)	3 ns	--	3 ns	--
Data hold time (Thold)	0 ns	--	0 ns	--

The measurements were taken at the 50% points under the following conditions.

• T = -40°C to 85°C, V = 5.0 V ±10%

• Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/4.5 V

The following I/O write time delays were measured.

Table 15-6. I/O Write Time Delays

Time Delay	Output Capacitance
	20 pF		70 pF
	min.	max.	min.	max.
Clock to address delay (Tadr)	--	8 ns	--	14 ns
Clock to memory chip select delay (TCSx)	--	8 ns	--	14 ns
Clock to I/O chip select delay (TIOCSx)	--	8 ns	--	14 ns
Clock to I/O write strobe delay (TIOWR)	--	6 ns	--	12 ns
Clock to I/O buffer enable delay (TBUFEN)	--	8 ns	--	14 ns
High Z to data valid relative to clock (TDHZV)	--	11 ns	--	17 ns
Data valid to high Z relative to clock (TDVHZ)	--	11 ns	--	17 ns

The measurements were taken at the 50% points under the same conditions that the I/O read delays were measured.

I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified.

Figure 15-4. I/O Read and Write Cycles--No Extra Wait States

Figure 15-5 shows the effect of adding an extra wait state to the memory read/write cycles. The effects are similar for the I/O bus read/write cycles.

Figure 15-5. Memory Read and Write with Wait States

Table 15-7 provides typical memory and external I/O parameters measured at 3.3 V.

Table 15-7. Memory and External I/O Read/Write Parameters at 3.3 V

Parameter		Description	Value
Read Parameters	Tadr	Time from CPU clock rising edge to address valid	Max.	10 ns @ 20 pF 19 ns @ 70 pF
	Tsetup	Data read setup time	Min.	3 ns
	Thold	Data read hold time	Min.	0 ns
Write Parameters	Tadr	Time from CPU clock rising edge to address valid	Max.	10 ns @ 20 pF 19 ns @ 70 pF
	Thold	Data write hold time from /WEx or /IOWR	Min.	½ CPU clock cycle

15.2 Current Consumption

Typical current is proportional to both clock frequency and voltage. The main oscillator requires approximately 6 mA at 5 V and 2 mA at 3 V independent of frequency. The basic current consumption for the processor exclusive of the oscillator at 5 V and 15 MHz is approximately 42 mA. The following formula can be used to compute the current consumption:

(2) I = (0.7)*(freq MHz)*(voltage) + (0.35)*(voltage - 0.86)²

The first term represents the current consumed by the processor, which is directly proportional to voltage and frequency. The second term is the current consumed by the main oscillator, which is approximately independent of frequency, but varies as the square of the voltage. This term is zero when the main oscillator is disabled. Some checkpoints for current consumption are provided in Table 15-8.

Table 15-8. Typical Current at Selected Frequencies and Voltages at 25°C

Clock Frequency (MHz)	Voltage (V)	Current (mA)
29.4912	5	109
22.11	5	83
14.7456	5	58
14.7456	3.3	36
7.3728	3.3	19
3.6864	3.3	11
1.8432	3.3	6
0.9216	3.3	4.2
0.4608	3.3	3.14
0.032 (sleepy mode)	5	0.280
0.032 (sleepy mode)	4	0.173
0.032 (sleepy mode)	3.3	0.113
0.032 (sleepy mode)	2.7	0.072

The current consumed by memory and other devices included in the system, including pullup resistors, outputs driving a load, and floating inputs, must be added to the figures in Table 15-8.

The 32.768 kHz clock oscillator and the associated real-time clock consume approximately 23 µA at 3 V. (At 2.25 V, when backed by a battery, the current consumption is approximately 11 µA.) The (typical) current consumed when the main power is off, and only the 32.768 kHz oscillator and clock are powered, is given by the formula

(3) current (µA) = 5.44*(V - 0.86)²

where V is the operating voltage. This is the current that must be supplied by a backup battery, not counting the current required by the associated circuits. The oscillator will not operate below approximately 1.3 V. The measurement from which the above formula was derived were made with a series resistor of 390 kW and load capacitors of 15 pF in the 32.768 kHz oscillator circuit. The shunt resistor was 10 MW.

If the processor is running at 32.768 kHz, then the added current to operate the processor at room temperature (main oscillator shut off) is given by:

(4) current (µA) = 7.5*(V²)

In low-power modes the current consumption is proportional to the square of the voltage. At 3.0 V this is approximately 67 µA. Add the 25 µA needed to operate the oscillator and the total current consumption will be approximately 92 µA with the processor operating at 32.768 kHz.

The current consumed by RAM or flash memory will be substantial and very significant at lower frequencies if auto powerdown flash or low-power RAM is not used. If low-power RAM is used to support the sleepy mode, the sleepy mode loop should be copied to RAM and executed in RAM. When trying to operate in an ultra low-power sleepy mode, it is important that no inputs be floating. Floating inputs consume substantial power. Keep in mind that port D open-drain outputs will create floating inputs if not pulled toward zero. Pullup resistors consume current and should be avoided or disabled in ultra low-power modes. When testing a sleepy mode of operation, it is advisable to connect an ammeter to make sure that no extra floating inputs or other current-consuming features are included in the setup.