Rabbit 2000 Microprocessor
User's Manual
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9. Parallel Ports

The Rabbit has five 8-bit parallel ports designated A, B, C, D and E. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are summarized below.

9.1 Parallel Port A

Parallel Port A has a single read/write register.

Table 9-1. Parallel Port A Registers
Register Name Mnemonic I/O address R/W Reset
Port A Data Register
PADR
0x30
R/W
xxxxxxxx
Slave Port Control Register
SPCR
0x24
R/W
0xx00000

Table 9-2. Parallel Port A Data Register Bit Functions
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PADR (R/W)
adr = 0x030
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0

This register should not be used if the slave port is enabled.

The slave port control register is used to control whether Parallel Port A is an output or an input. To make the port an input, store 0x080 in the SPCR (slave port control register). To make the port an output, store 0x084 in SPCR. Parallel Port A is set up as an input port on reset.

When the port is read, the value read reflects the voltages on the pins, "1" for high and "0" for low. This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage.

9.2 Parallel Port B

Parallel Port B, shown in Table 9-4, has six inputs and two outputs when used exclusively as a parallel port.

Table 9-3. Parallel Port B Registers
Register Name Mnemonic I/O address R/W Reset
Port B Data Register
PBDR
0x40
R/W
00xxxxxx

Table 9-4. Parallel Port B Data Register PBDR (adr = 0x040)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read
Echo drive
Echo drive
PB5 in
PB4 in
PB3 in
PB2 in
PB1 in
PB0 in
Write
PB7
PB6
x
x
x
x
x
x

When the slave port is enabled, parallel port lines PB2-PB7 are assigned to various slave port functions. However, it is still possible to read PB0-PB5 using the Port B data register even when lines PB2-PB7 are used for the slave port. It is also possible to read the signal driving PB6 and PB7 (this signal is on the signaling lines from the slave port logic).

Regardless of whether the slave port is enabled, PB0 reflects the input of the pin unless serial port B has its internal clock enabled, which causes this line to be driven by the serial port clock. PB1 reflects the input of the pin unless serial port A has its internal clock enabled.

On reset the output bits 6 and 7 are reset and the value output on pins PB6 and PB7 (package pins 99, 100) will also be low.

9.3 Parallel Port C

Parallel port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5, and PC7, are inputs. When the data register is read, bits 1,3,5,7 return the value of the voltage on the pin. Bits 0,2,4,6 return the value of the signal driving the output buffers. The signal driving the output buffers and the value of the output pin are normally the same. Either the Port C data register is driving these pins or one of the serial port transmit lines is driving the pin. The bits set in the PCFR Parallel Port C Function Register identify whether the data register or the serial port transmit lines were driving the pins.

Table 9-5. Parallel Port C Registers
Register Name Mnemonic I/O address R/W Reset
Port C Data Register
PCDR
0x50
R/W
x0x0x0x0
Port C Function Register
PCFR
0x55
W
x0x0x0x0

Table 9-6. Parallel Port C Data Register and Function Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PCDR (r)
adr = 0x050
PC7 in
Echo drive
PC5 in
Echo drive
PC3 in
Echo drive
PC1 in
Echo drive
PCDR (w)
adr = 0x050
x
PC6
x
PC4
x
PC2
x
PC0
PCFR (w)
adr = 0x055
x
Drive TXA
x
Drive TXB
x
Drive
TXC
x
Drive TXD

Parallel port C shares its pins with the four serial ports. The parallel port input pins may also serve as serial port inputs. (Serial ports A and B can alternately use bits 7 and 5 respectively in Port D as inputs, and the source of the serial port inputs for these serial ports depends on the setup of the corresponding serial port control register.) When serving as serial inputs, the data lines can still be read from the parallel port C data register. The parallel port outputs can be selected to be serial port outputs by storing bits in the corresponding positions of the Port C Function register (PCFR). When a parallel port output pin is selected to be a serial port output, the value stored in the data register is ignored. On reset the active (even-numbered) function register bits and data register bits are zeroed. This causes the port to output zeros on the four output bits.

9.4 Parallel Port D

Parallel port D, shown in Figure 9-1, has eight pins that can programmed individually to be inputs and outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses. In addition, port D outputs have a higher drive capability. Port D bits 4 and 5 can be used as alternate bits for serial port B, and bits 6 and 7 can be used as alternate bits for serial port A. Alternate serial port bit assignments make it possible for the same serial port to connect to different communications lines that are not operating at the same time.

On reset, the data direction register is zeroed, making all pins inputs. In addition bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with port D are not initialized on reset.

Table 9-7. Parallel Port D Registers
Register Name Mnemonic I/O address R/W Reset
Port D Data Register
PDDR
0x60
R/W
xxxxxxxx
Port D Drive Control Register
PDDCR
0x66
W
xxxxxxxx
Port D Data Direction Register
PDDDR
0x67
W
00000000
Port D Function Register
PDFR
0x65
W
xxxxxxxx
Port D Control Register
PDCR
0x64
W
xx00xx00
Port D Bit 0 Register
PDB0R
0x68
W
xxxxxxxx
Port D Bit 1 Register
PDB1R
0x69
W
xxxxxxxx
Port D Bit 2 Register
PDB2R
0x6A
W
xxxxxxxx
Port D Bit 3 Register
PDB3R
0x6B
W
xxxxxxxx
Port D Bit 4 Register
PDB4R
0x6C
W
xxxxxxxx
Port D Bit 5 Register
PDB5R
0x6D
W
xxxxxxxx
Port D Bit 6 Register
PDB6R
0x6E
W
xxxxxxxx
Port D Bit 7 Register
PDB7R
0x6F
W
xxxxxxxx

The following registers are described in Table 9-8 and in Table 9-9.


Figure 9-1. Parallel Port D Block Diagram
Table 9-8. Parallel Port D Registers
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PDDR (R/W)
adr = 0x060
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDDCR (W)
adr = 0x066
out =
open drain
out =
open drain
out =
open drain
out =
open drain
out =
open drain
out =
open drain
out =
open drain
out =
open drain
PDFR (W)
adr = 0x065
x
alt TXA
x
alt TXB
x
x
x
x
PDDDR (W)
adr = 0x067
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
PDB0R (W)
adr = 0x068
x
x
x
x
x
x
x
PD0
PDB1R (W)
adr = 0x069
x
x
x
x
x
x
PD1
x
PDB2R (W)
adr = 0x06A
x
x
x
x
x
PD2
x
x
PDB3R (W)
adr =0x 06B
x
x
x
x
PD3
x
x
x
PDB4R (W)
adr = 0x06C
x
x
x
PD4
x
x
x
x
PDB5R (W)
adr = 0x06D
x
x
PD5
x
x
x
x
x
PDB6R (W)
adr = 0x06E
x
PD6
x
x
x
x
x
x
PDB7R (W)
adr = 0x06F
PD7
x
x
x
x
x
x
x

Table 9-9. Parallel Port D Control Register (adr = 0x064)
Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0
x
00--clock upper nibble on pclk/2
01--clock on timer A1
10--clock on timer B1
11--clock on timer B2
x
00--clock lower nibble on pclk/2
01--clock on timer A1
10--clock on timer B1
11--clock on timer B2

9.5 Parallel Port E

Parallel port E, shown in Figure 9-2, has eight I/O pins that can be individually programmed as inputs or outputs. Port E has a higher drive than most of the other ports. PE7 is used as the slave port chip select when the slave port is enabled. Each of the port E outputs can be configured as an I/O strobe. In addition, four of the port E lines can be used as interrupt request inputs. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses.


Figure 9-2. Parallel Port E Block Diagram

Table 9-10. Parallel Port E Registers
Register Name Mnemonic I/O address R/W Reset
Port E Data Register
PEDR
0x70
R/W
xxxxxxxx
Port E Control Register
PECR
0x74
W
xx00xx00
Port E Function Register
PEFR
0x75
W
00000000
Port E Data Direction Register
PEDDR
0x77
W
00000000
Port E Bit 0 Register
PEB0R
0x78
W
xxxxxxxx
Port E Bit 1 Register
PEB1R
0x79
W
xxxxxxxx
Port E Bit 2 Register
PEB2R
0x7A
W
xxxxxxxx
Port E Bit 3 Register
PEB3R
0x7B
W
xxxxxxxx
Port E Bit 4 Register
PEB4R
0x7C
W
xxxxxxxx
Port E Bit 5 Register
PEB5R
0x7D
W
xxxxxxxx
Port E Bit 6 Register
PEB6R
0x7E
W
xxxxxxxx
Port E Bit 7 Register
PEB7R
0x7F
W
xxxxxxxx

The following registers are described in Table 9-11 and in Table 9-12.

Table 9-11. Parallel Port E Registers
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PEDR (R/W)
adr = 0x070
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PEFR (W)
adr = 0x075
alt /I7
alt /I6
alt /I5
alt /I4
alt /I3
alt /I2
alt /I1
alt /I0
PEDDR (W) adr = 0x077
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
PEB0R (W)
adr = 0x078
x
x
x
x
x
x
x
PE0
PEB1R (W)
adr = 0x079
x
x
x
x
x
x
PE1
x
PEB2R (W)
adr = 0x07A
x
x
x
x
x
PE2
x
x
PEB3R (W)
adr = 0x07B
x
x
x
x
PE3
x
x
x
PEB4R (W)
adr = 0x07C
x
x
x
PE4
x
x
x
x
PEB5R (W)
adr = 0x07D
x
x
PE5
x
x
x
x
x
PEB6R (W)
adr = 0x07E
x
PE6
x
x
x
x
x
x
PEB7R (W)
adr = 0x07F
PE7
x
x
x
x
x
x
x

Table 9-12. Parallel Port E Control Register (adr = 0x074)
Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0
x
00--clock upper nibble on pclk/2
01--clock on timer A1
10--clock on timer B1
11--clock on timer B2
x
00--clock lower nibble on pclk/2
01--clock on timer A1
10--clock on timer B1
11--clock on timer B2


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