Appendix B. Power Management

Appendix B describes the power circuitry distributed on the TCP/IP Development Board.

B.1 Power Supplies

Power is supplied to the TCP/IP Development Board from an external source either through header J7 or from another TCP/IP Development Board through header J5, the RJ-12 jack.

The TCP/IP Development Board itself is protected against reverse polarity by Shottky diodes at D6 and D7 as shown in Figure B-1. The Shottky diode has a low forward voltage drop, 0.3 V, which keeps the minimum DCIN required to power the TCP/IP Development Board lower than a normal silicon diode would allow.

Figure B-1. TCP/IP Development Board Power Supply Schematic

Capacitor C28 provides surge current protection for the voltage regulator, and allows the external power supply to be located some distance away from the TCP/IP Development Board. A switching power regulator is used. The input voltage range is from 9 V to 40 V.

B.2 Batteries and External Battery Connections

A battery board with a 1000 mA·h lithium coin cell is available to provide power to the real-time clock and SRAM when external power is removed from the circuit. This allows the TCP/IP Development Board to continue to keep track of time and preserves the SRAM memory contents.

Figure B-2 shows the battery-board circuit.

Figure B-2. Battery-Board Circuit

Alternatively, starting with the 175-0206 version of the TCP/IP Development Board, there is provision to add a soldered-in battery directly on the TCP/IP Development Board.

The drain on the battery is typically less than 20 µA when there is no external power applied. The battery can last more than 5 years:

The drain on the battery is typically less than 4 µA when external power is applied. The battery can last for its full shelf life:

Since the shelf life of the battery is 10 years, the battery can last for its full shelf life when external power is applied to the TCP/IP Development Board.

B.2.1 Battery-Backup Circuit

The battery-backup circuit serves two purposes:

• It reduces the battery voltage to the real-time clock, thereby reducing the current consumed by the real-time clock and lengthening the battery life.
• It ensures that current can flow only out of the battery to prevent charging the battery.

Figure B-3 shows the battery-backup circuitry on the TCP/IP Development Board.

Figure B-3. TCP/IP Development Board Battery Backup Circuit

The battery-backup circuit serves three purposes:

• It reduces the battery voltage to the SRAM and to the real-time clock, thereby limiting the current consumed by the real-time clock and lengthening the battery life.
• It ensures that current can flow only out of the battery to prevent charging the battery.
• A voltage, VOSC, is supplied to U13, which keeps the 32.768 kHz oscillator working when the voltage begins to drop.

VRAM and Vcc are nearly equal (<100 mV, typically 10 mV) when power is supplied to the TCP/IP Development Board. VRAM is also available on pin 34 of header J2 to facilitate battery backup of the external circuit. Note that the recommended minimum resistive load at VRAM is 100 kW, and new battery life calculations should be done to take external loading into account.

B.2.2 Power to VRAM Switch

The VRAM switch, shown in Figure B-4, allows the battery backup to provide power when the external power goes off. The switch provides an isolation between Vcc and the battery when Vcc goes low. This prevents the Vcc line from draining the battery.

Figure B-4. VRAM Switch

Transistor Q3 is needed to provide a very small voltage drop between Vcc and VRAM (<100 mV, typically 10 mV) so that the processor lines powered by Vcc will not have a significantly different voltage than VRAM.

When the TCP/IP Development Board is not resetting (pin 2 on U4 is high), the /RES line will be high. This turns on Q4, causing its collector to go low. This turns on Q3, allowing VRAM to nearly equal Vcc.

When the TCP/IP Development Board is resetting, the /RES line will go low. This turns off Q3 and Q4, providing an isolation between Vcc and VRAM.

The battery backup circuit keeps VRAM from dropping below 2 V.

B.2.3 Reset Generator

The TCP/IP Development Board uses a reset generator, U2, to reset the Rabbit 2000 microprocessor when the voltage drops below the voltage necessary for reliable operation. The reset occurs between 4.50 V and 4.75 V, typically 4.63 V.

B.2.4 Installing/Replacing the Backup-Battery Board

An optional pluggable backup-battery board is available from Rabbit Semiconductor.

To install the backup-battery board, align the battery board over the outline as shown in Figure B-5, and plug it in. Be careful to align the connectors and the backup battery board. Fasten the backup board using a 4-40 × 3/16 screw and lockwasher.

NOTE	Before replacing the backup-battery board, make sure that the TCP/IP Development Board is receiving power from the standard power supply. This makes sure that data in RAM are not lost when the battery backup board is removed temporarily.

To replace the backup-battery board, remove the screw and unplug the old battery board. Then install a replacement backup-battery board.

Figure B-5. Installing Backup Battery Board

Do not attempt to recharge the old battery and do not dispose of it in regular trash to avoid any risk of explosion or fire. You may either return the old backup battery board to Rabbit Semiconductor for recycling or send the battery yourself to an approved recycling facility.

B.3 Chip Select Circuit

Figure B-6 shows a schematic of the chip select circuit.

Figure B-6. Chip Select Circuit

The current drain on the battery in a battery-backed circuit must be kept at a minimum. When the TCP/IP Development Board is not powered, the battery keeps the SRAM memory contents and the real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces power consumption. This powerdown mode is activated by raising the chip select (CS) signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is required for data retention in powerdown mode. Thus, when power is removed from the circuit, the battery voltage needs to be provided to both the SRAM power pin and to the CS signal line. The CS control circuit accomplishes this task for the CS signal line.

In a powered-up condition, the CS control circuit must allow the processor's chip select signal /CS1 to control the SRAM's CS signal /CSRAM. So, with power applied, /CSRAM must be the same signal as /CS1, and with power removed, /CSRAM must be held high (but only needs to be battery voltage high). Q5 and Q6 are MOSFET transistors with opposing polarity. They are both turned on when power is applied to the circuit. They allow the CS signal to pass from the processor to the SRAM so that the processor can periodically access the SRAM. When power is removed from the circuit, the transistors will turn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 kW pullup resistor to VRAM (R29). This pullup resistor keeps /CSRAM at the VRAM voltage level (which under no power condition is the backup battery's regulated voltage at a little more than 2 V).

Transistors Q5 and Q6 are of opposite polarity so that a rail-to-rail voltage can be passed. When the /CS1 voltage is low, Q5 will conduct. When the /CS1 voltage is high, Q6 will conduct. It takes time for the transistors to turn on, creating a propagation delay. This delay is typically very small, about 10 ns to 15 ns.

The signal that turns the transistors on is a high on the processor's reset line, /RES. When the TCP/IP Development Board is not in reset, the reset line will be high, turning on n-channel Q5 and Q7. Q7 is a simple inverter needed to turn on Q6, a p-channel MOSFET. When a reset occurs, the /RES line will go low. This will cause C14 to discharge through R32 and R34. This small delay (about 160 µs) ensures that there is adequate time for the processor to write any last byte pending to the SRAM before the processor puts itself into a reset state. When coming out of reset, CS will be enabled very quickly because D1 conducts to charge capacitor C14.