Appendix E. Smart Star Slot Address Layout

Appendix F provides information about the register addresses for the various I/O card slots on the backplane. The information in this appendix will be of interest to more advanced users.

The slots on the Smart Star backplane are accessed as external registers via the Rabbit 2000's assembly IOE prefix or via standard Rabbit BIOS functions. More convenient functions specific to the Smart Star control system have been written to provide more flexibility; for example, there is now a provision for the automatic update of shadow registers for each slot and for each register.

The Smart Star design routes four address bits to each slot, providing 16 register addresses for each slot. These bits are passed through as bits 0-3 of the register address. The slot number itself is assigned to bits 6-8 of the address. In addition, the backplane design requires that bits 13 and 14 be high and that bit 9 be low. The simplest way to enforce this is to use a base address of 0x6000. Table E-1 provides the address layout for accessing the Smart Star slots, where Sn is the binary representation of the slot number (0-6), Rn is the binary representation of the register numbers (0-15), and X means the value does not matter.

Table E-1. Smart Star External Register Address Bitmap

A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1	A0
0	1	1	0	X	X	0	S2	S1	S0	X	X	R3	R2	R1	R0

This bit mapping of the external register address provides the register addresses for each slot as listed in Table E-2.

Table E-2. Slot External Register Addresses

Slot Number	Address Range
0	0x6000-0x600F
1	0x6040-0x604F
2	0x6080-0x608F
3	0x60C0-0x60CF
4	0x6100-0x610F
5	0x6140-0x614F
6	0x6180-0x618F

E.1 Digital I/O Card Channel Layout

The digital I/O card layout is complicated by the standard Z-World method of minimizing chip layout while adding channel arrangement flexibility. In particular, the nibble-wise layout of digital input channels requires fewer chips if fewer channels are desired. This is a common feature on Z-World products and should not surprise most users. The digital output channel layout is straightforward.

It is also possible to access the digital I/O channels in banks of eight channels. This method is significantly faster than reading eight channels one at a time, and so was included in the API.

Table E-3. Digital I/O Card Bank/Channel Mapping

Local Board Address	Input Bank	Output Bank	Input Channels	Output Channels
0x00	0		0-3/8-11
0x01	2		4-7/12-15
0x02		1		0-7
0x03		2		8-15

E.2 A/D Converter Card Channel Layout

The A/D converter card contains a single 11-input 12-bit A/D converter, TLC2543. The method of interfacing to this chip is a combination of single-bit writes via board registers and synchronous clocked serial access via the CPU card's Serial Port B, which is extended across all eight slots. In addition, a serial EEPROM is installed on the A/D converter card to store the calibration constants.

Table E-4. A/D Converter Card Control Registers

Address	Data Bits	Value	Description
0x0	Write D7-D0	D7-D4 selects input channel, D3-D0 selects conversion channel	Load A/D converter with data byte
0x0	Read D1	0	A/D converter end of conversion signal
		1	A/D converter busy
0x1	Write D0	0	Enable A/D conversion
		1	Disable A/D conversion
0x2	Write D0	0	EEPROM clock line low
		1	EEPROM clock line high
0x3	Write D0	0	EEPROM data line low
		1	EEPROM data line high
0x0	Read D2	0	EEPROM acknowledge signal
		1	EEPROM busy

E.3 D/A Converter Card Channel Layout

The D/A converter card contains four two-channel 12-bit D/A converters, TLV5618, to produce 8 analog output channels. Each channel is accessed by the slot, channel and device addressing scheme. The D/A converter card also has an EEPROM to store calibration constants.

Table E-5. D/A Converter Card Control Registers

Address	Data Bits	Value	Description
0x0	D0	0	D/A converter clock line low
		1	D/A converter clock line high
	D1	X	D/A converter data input line
	D2	0	D/A converter chip select channels 0 and 1
	D3	0	D/A converter chip select channels 2 and 3
	D4	0	D/A converter chip select channels 4 and 5
	D5	0	D/A converter chip select channels 6 and 7
	D6	0	EEPROM clock line low
		1	EEPROM clock line high
	D7	X	EEPROM data line

External reads and writes (/IORD and /IOWR) control the data direction.

E.4 Relay Card Channel Layout

The relay card layout is complemented by the standard Z-World method of minimizing chip layout while adding channel arrangement flexibility. In particular, the nibble-wise layout of the relay channels requires fewer chips if fewer channels are desired. This is a common feature on Z-World products and should not surprise most users. The relay channel layout is straightforward.

Table E-6. Relay Card Channel Mapping

Local Board Address	SR9500 Relay Channels	SR9510 Relay Channels
0x00	REL0	REL0
0x01	REL1	REL1
0x02	REL2	REL2
0x03	REL3	REL3
0x04	REL4	REL4
0x05	REL5	REL5
0x06	--	REL6
0x07	--	REL7

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