5. Pin Assignments and Functions

5.1 Package Schematic and Pinout

Figure 5-1. Package Outline and Pin Assignments

5.2 Package Mechanical Dimensions

Figure 5-2 shows the mechanical dimensions of the Rabbit 3000 LQFP package.

Figure 5-2. Mechanical Dimensions Rabbit LQFP Package

Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pattern Standard, IPC, Northbrook, IL, 1999.

Figure 5-3. PC Board Land Pattern for Rabbit 3000 128-pin LQFP

5.2.1 Ball Grid Array Pinout

Rabbit 3000 AT56C55-IZ1T

128 Thin Map TFBGA

10x10 Body, 0.8 mm pitch

Figure 5-4. Ball Grid Array Pinout Looking Through the Top of Package

5.3 Rabbit Pin Descriptions

Table 5-1 lists all the pins on the device, along with their direction, function, and pin number on the package.

Table 5-1. Rabbit Pin Descriptions 

Pin Group	Pin Name	Direction	Function	Pin Numbers LQFP	Pin Numbers TFBGA
Hardware	CLK	Output	Internal Clock	2	B1
	CLK32K	Input	32kHz Oscillator In	49
	/RESET	Input	Master Reset	46
	RESOUT	Output	Reset Output	50
	XTALA1	Input	Main Oscillator In	113	B7
	XTALA2	Output	Main Oscillator Out	114	A7
CPU Buses	ADDR[19:0]	Output	Address Bus	various
	DATA[7:0]	Bidirectional	Data Bus	19-18, 15-10
Status/Control	/WDTOUT	Output	WDT Time-Out	43
	STATUS	Output	Instruction Fetch First Byte	4
	SMODE[1:0]	Input	Bootstrap Mode Select	[44,45]
Memory Chip Selects	/CS0	Output	Memory Chip Select 0	7
	/CS1	Output	Memory Chip Select 1	47
	/CS2	Output	Memory Chip Select 2	3
Memory Output Enables	/OE0	Output	Memory Output Enable 0	5
	/OE1	Output	Memory Output Enable 1	95
Memory Write Enables	/WE0	Output	Memory Write Enable 0	86
	/WE1	Output	Memory Write Enable 1	99
I/O Control	/BUFEN	Output	I/O Buffer Enable	42
	/IORD	Output	I/O Read Enable	41
	/IOWR	Output	I/O Write Enable	40
I/O ports	PA[7:0]	Input / Output	I/O Port A	104-111
	PB[7:0]	Input / Output	I/O Port B	116-123
	PC[7:0]	4 In / 4 Out	I/O Port C	75,74, 71-66
	PD[7:0]	Input / Output	I/O Port D	59-52
	PE[7:0]	Input / Output	I/O Port E	33, 34,31-26
	PF[7:0]	Input / Output	I/O Port F	100-103, 124-127
	PG[7:0]	Input / Output	I/O Port G	63-60, 38-36
Power, processor core	VDDCORE		+3.3V	8, 24, 72, 88
Power Processor I/O Ring	VDDIO		+3.3V	1, 17, 33, 65, 81, 97, 115
Power Battery Backup	VBAT		+3.3V or battery	47
Ground Processor Core	VSSCORE		Ground	9, 25, 73, 89
Ground Processor I/O Ring	VSSIO		Ground	16, 32, 48, 64, 80, 96, 112, 128

5.4 Bus Timing

The external bus has essentially the same timing for memory cycles or I/O cycles. A memory cycle begins with the chip select and the address lines. One clock later, the output enable is asserted for a read. The output data and the write enable are asserted for a write.

Figure 5-5. Bus Timing Read and Write

In some cases, the timing shown in Figure 5-5 may be prefixed by a false memory access during the first clock, which is followed by the access sequence shown in Figure 5-5. In this case, the address and often the chip select will change values after one clock and assume the final values for the memory to be actually accessed. Output enable and write enable are always delayed by one clock from the time the final, stable address and chip select are enabled. Normally the false memory access attempts to start another instruction access cycle, which is aborted after one clock when the processor realizes that a read data or write data bus cycle is needed. The user should not attempt a design that uses the chip select or a memory address as a clock or state changing signal without taking this into consideration.

5.5 Description of Pins with Alternate Functions

Table 5-2. Pins With Alternate Functions 

Pin Name	Output Function	Input Function	Input Capture Option
PA[7:0]	SLAVE_D[7:0], IODat[7:0]	SLAVE_D[7:0], IODat[7:0]
PB[7]	SLAVE_ATTNB, IOAddr[5]
PB[6]	IOAddr[4]
PB[5]	IOAddr[3]	SLAVE_AD[1]
PB[4]	IOAddr[2]	SLAVE_AD[0]
PB[3]	IOAddr[1]	SLAVE_RDB
PB[2]	IOAddr[0]	SLAVE_WRB
PB[1]	CLKA	CLKA
PB[0]	CLKB	CLKB
PC[7]	n/a	RXA	yes
PC[6]	TXA	n/a
PC[5]	n/a	RXB	yes
PC[4]	TXB	n/a
PC[3]	n/a	RXC	yes
PC[2]	TXC	n/a
PC[1]	n/a	RXD	yes
PC[0]	TXD	n/a
PD[7]		ALT_RXA	yes
PD[6]	ALT_TXA
PD[5]		ALT_RXB	yes
PD[4]	ALT_TXB
PD[3]			yes
PD[2]
PD[1]			yes
PD[0]
PE[7]	IOCTLB[7]	/SCS (slave chip select)
PE[6]	IOCTLB[6]
PE[5]	IOCTLB[5]	INT[1]
PE[4]	IOCTLB[4]	INT[0]
PE[3]	IOCTLB[3]
PE[2]	IOCTLB[2]
PE[1]	IOCTLB[1]	INT[1]
PE[0]	IOCTLB[0]	INT[0]
PF[7]	PWM[3]	QRD2_I	yes
PF[6]	PWM[2]	QRD2_Q
PF[5]	PWM[1]	QRD1_I	yes
PF[4]	PWM[0]	QRD1_Q
PF[3]		QRD2_I	yes
PF[2]		QRD2_Q
PF[1]	CLKC	QRD1_I, CLKC	yes
PF[0]	CLKD	QRD1_Q, CLKD
PG[7]		RXE	yes
PG[6]	TXE
PG[5]	RCLKE	RCLKE	yes
PG[4]	TCLKE	TCLKE
PG[3]		RXF
PG[2]	TXF
PG[1]		RCLKF
PG[0]	TCLKF

5.6 DC Characteristics

5.6.1 3.3 Volts

Table 5-3 outlines the DC characteristics for the Rabbit at 3.3 V over the recommended operating temperature range from Ta = -40°C to +85°C, VDD = 3.0 V to 3.6 V.

Table 5-3. 3.3 Volt DC Characteristics

Symbol	Parameter	Test Conditions	Min	Typ	Max	Units
	Maximum input voltage	Except oscillator buffer			5.5	V
VIL	CMOS Input Low Voltage				0.3 x VDD	V
VIH	CMOS Input High Voltage		0.7 x VDD			V
VT	CMOS Switching Threshold	VDD = 3.3 V, 25°C		1.65		V

5.7 I/O Buffer Sourcing and Sinking Limit

Unless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking 6 mA (preliminary) of current per pin at full AC switching speed. The limits are related to the maximum sustained current permitted by the metallization on the die.