1. Introduction

Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium-scale controllers. The first microprocessor was the Rabbit 2000. The second microprocessor, now available, is the Rabbit 3000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small controllers. The Rabbit shares a similar architecture and a high degree of compatibility with these microprocessors, but it is a vast improvement.

The Rabbit 3000 has been designed in close cooperation with Z-World, Inc., a long-time manufacturer of low-cost single-board computers. Z-World's products are supported by an innovative C-language development system (Dynamic C). Z-World is providing the software development tools for the Rabbit 3000.

The Rabbit 3000 is easy to use. Hardware and software interfaces are as uncluttered and are as foolproof as possible. The Rabbit has outstanding computation speed for a microprocessor with an 8-bit bus. This is because the Z80-derived instruction set is very compact, and the timing of the memory interface allows higher clock speeds for a given memory speed.

Microprocessor hardware and software development is easy for Rabbit users. In-circuit emulators are not needed and will not be missed by the Rabbit developer. Software development is accomplished by connecting a simple interface cable from a PC serial port to the Rabbit-based target system or by performing software development and debugging over a network or the Internet using interfaces and tools provided by Rabbit Semiconductor.

1.1 Features and Specifications Rabbit 3000

• 128-pin PQFP package. Operating voltage 1.8 V to 3.6 V. Clock speed to 54+ MHz. All specifications are given for both industrial and commercial temperature and voltage ranges. Rabbit microprocessors are low-cost.

• Industrial specifications are for 3.3 V ±10% and a temperature range from -40°C to +85°C. Modified commercial specifications are for a voltage variation of 5% and a temperature range from -40°C to 70°C.

• 1-megabyte code-data space allows C programs with 50,000+ lines of code. The extended Z80-style instruction set is C-friendly, with short and fast opcodes for the most important C operations.

• Four levels of interrupt priority make a fast interrupt response practical for critical applications. The maximum time to the first instruction of an interrupt routine is about 0.5 µs at a clock speed of 50 MHz.

• Access to I/O devices is accomplished by using memory access instructions with an I/O prefix. Access to I/O devices is thus faster and easier compared to processors with a distinct and narrow I/O instruction set. As an option the auxiliary I/O bus can be enabled to use separate pins for address and data, allowing the I/O bus to have a greater physical extent with less EMI and less conflict with the requirements of the fast memory bus.(Further described below.)

• Hardware design is simple. Up to six static memory chips (such as RAM and flash memory) connect directly to the microprocessor with no glue logic. A memory-access time of 55 ns suffices to support up to a 30 MHz clock with no wait states; with a 30 ns memory-access time, a clock speed of up to 50 MHz is possible with no wait states. Most I/O devices may be connected without glue logic.

• The memory read cycle is two clocks long. The write cycle is 3 clocks long. A clean memory and I/O cycle completely avoid the possibility of bus fights. Peripheral I/O devices can usually be interfaced in a glueless fashion using. A built-in clock doubler allows ½-frequency crystals to be used.

• EMI reduction features reduce EMI levels by as much as 25 dB compared to other similar microprocessors. Separate power pins for the on-chip I/O buffers prevent high-frequency noise generated in the processor core from propagating to the signal output pins. A built-in clock spectrum spreader reduces electromagnetic interference and facilitates passing EMI tests to prove compliance with government regulatory requirements. As a consequence, the designer of a Rabbit-3000-based system can be assured of passing FCC or CE EMI tests as long as minimal design precautions are followed.

• The Rabbit may be cold-booted via a serial port or the parallel access slave port. This means that flash program memory may be soldered in unprogrammed, and can be reprogrammed at any time without any assumption of an existing program or BIOS. A Rabbit that is slaved to a master processor can operate entirely with volatile RAM, depending on the master for a cold program boot.

• There are 56 parallel I/O lines (shared with serial ports). Some I/O lines are timer synchronized, which permits precisely timed edges and pulses to be generated under combined hardware and software control. Pulse-width modulation outputs are implemented in addition to the timer-synchronization feature (see below).

• Four pulse width modulated (PWM) outputs are implemented by special hardware. The repetition frequency and the duty cycle can be varied over a wide range. The resolution of the duty cycle is 1 part in 1024.

• There are six serial ports. All six serial ports can operate asynchronously in a variety of commonly used operating modes. Four of the six ports (designated A, B, C, D) support clocked serial communications suitable for interfacing with "SPI" devices and various similar devices such as A/D converters and memories that use a clocked serial protocol. Two of the ports, E and F, support HDLC/SDLC synchronous communication. These ports have a 4-byte FIFO and can operate at a high data rate. Ports E and F also have a digital phase-locked loop for clock recovery, and support popular data-encoding methods. High data rates are supported by all six serial ports. The asynchronous ports also support the 9th bit network scheme as well as infrared transmission using the IRDA protocol. The IRDA protocol is also supported in SDLC format by the two ports that support SDLC.

• A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of communication. Independent strobes and interrupts are used to control the slave port in both directions. Only a Rabbit and a RAM chip are needed to construct a complete slave system, if the clock and reset control are shared with the master processor

• There is an option to enable an auxiliary I/O bus that is separate from the memory bus. The auxiliary I/O bus toggles only on I/O instructions. It reduces EMI and speeds the operation of the memory bus, which only has to connect to memory chips when the auxiliary I/O bus is used to connect I/O devices. This important feature makes memory design easy and allows a more relaxed approach to interfacing I/O devices.

• The built-in battery-backable time/date clock uses an external 32.768 kHz crystal oscillator. The suggested model circuit for the external oscillator utilizes a single "tiny logic" active component. The time/date clock can be used to provide periodic interrupts every 488 µs. Typical battery current consumption is about 3 µA.

• Numerous timers and counters can be used to generate interrupts, baud rate clocks, and timing for pulse generation.

• Two input-capture channels can be used to measure the width of pulses or to record the times at which a series of events take place. Each capture channel has a 16-bit counter and can take input from one or two pins selected from any of 16 pins.

• Two quadrature decoder units accept input from incremental optical shaft encoders. These units can be used to track the motion of a rotating shaft or similar device.

• The built-in main clock oscillator uses an external crystal or a ceramic resonator. Typical crystal or resonator frequencies are in the range of 1.8 MHz to 30 MHz. Since precision timing is available from the separate 32.768 kHz oscillator, a low-cost ceramic resonator with ½ percent error is generally satisfactory. The clock can be doubled or divided down to modify speed and power dynamically. The I/O clock, which clocks the serial ports, is divided separately so as not to affect baud rates and timers when the processor clock is divided or multiplied. For ultra low power operation, the processor clock can be driven from the separate 32.768 kHz oscillator and the main oscillator can be powered down. This allows the processor to operate at approximately between 20 and 100 µA and still execute instructions at the rate of up to 10,000 instructions per second. The 32.768 kHz clock can also be divided by 2, 4, 8 or 16 to reduce power. This "sleepy mode" is a powerful alternative to sleep modes of operation used by other processors.

• Processor current requirement is approximately 65 mA at 30 MHz and 3.3 V. The current is proportional to voltage and clock speed--at 1.8 V and 3.84 MHz the current would be about 5 mA, and at 1 MHz the current is reduced to about 1 mA.

• To allow extreme low power operation there are options to reduce the duty cycle of memories when running at low clock speeds by only enabling the chip select for a brief period, long enough to complete a read. This greatly reduces the power used by flash memory when operating at low clock speeds.

• The excellent floating-point performance is due to a tightly coded library and powerful processing capability. For example, a 50 MHz clock takes 7 µs for a floating add, 7 µs for a multiply, and 20 µs for a square root. In comparison, a 386EX processor running with an 8-bit bus at 25 MHz and using Borland C is about 20 times slower.

• There is a built-in watchdog timer.

• The standard 10-pin programming port eliminates the need for in-circuit emulators. A very simple 10-pin connector can be used to download and debug software using Z-World's Dynamic C and a simple connection to a PC serial port. The incremental cost of the programming port is extremely small.

Figure 1-1 shows a block diagram of the Rabbit.

Figure 1-1. Rabbit 3000 Block Diagram

1.2 Summary of Rabbit 3000 Advantages

• The glueless architecture makes it is easy to design the hardware system.

• There are a lot of serial ports and they can communicate very fast.

• Precision pulse and edge generation is a standard feature.

• EMI is at extremely low levels.

• Interrupts can have multiple priorities.

• Processor speed and power consumption are under program control.

• The ultra low power mode can perform computations and execute logical tests since the processor continues to execute, albeit at 32 kHz or even as slow as 2 kHz.

• The Rabbit may be used to create an intelligent peripheral or a slave processor. For example, protocol stacks can be off loaded to a Rabbit slave. The master can be any processor.

• The Rabbit can be cold-booted so unprogrammed flash memory can be soldered in place.

• You can write serious software, be it 1,000 or 50,000 lines of C code. The tools are there and they are low in cost.

• If you know the Z80 or Z180, you know most of the Rabbit.

• A simple 10-pin programming interface replaces in-circuit emulators and PROM programmers.

• The battery-backable time/date clock is included.

• The standard Rabbit chip is made to industrial temperature and voltage specifications.

• The Rabbit 3000 is backed by extensive software development tools and libraries, especially in the area of networking and embedded Internet.

1.3 Differences Rabbit 3000 vs. Rabbit 2000

For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rabbit 3000 is contrasted with the Rabbit 2000 in the table below.

Feature	Rabbit 3000	Rabbit 2000
Maximum clock speed	54 MHz	30 MHz
Maximum crystal frequency main oscillator (may be doubled internally)	30 MHz	32 MHz
32.768 kHz crystal oscillator	External	Internal
Maximum operating voltage	3.6 V	5.5 V
Maximum I/O input voltage	5.5 V	5.5 V
Current consumption	2 mA/MHz @ 3.3 V	4 mA/MHz @5 V
Number of package pins	128	100
Size of package	16 x 16 1.5 mm LQFP 10 x 10 x 1.2 mm TFBGA	24 × 18 x 3 mm PQFP
Spacing between package pins	0.4 mm (16 mils) LQFP 0.8 mm TFBGA	0.65 mm (26 mils) PQFP
Separate power and ground for I/O buffers (EMI reduction)	Yes	No
Clock Spectrum Spreader (EMI reduction)	Yes	To be retrofitted in future version.
Clock Modes	1x, 2x, /2, /3, /4, /6, /8	1x, 2x, /4, /8
Power Down Modes	Sleepy (32 kHz) Ultra-Sleepy (16, 8, 2 kHz)	Sleepy (32 kHz)
Low Power Memory Control (Chip Select)	Short CS (CLK /4 /6 /8) Self Timed (32,16,8,2 kHz)	None
Extended memory timing for high freq. operation	Yes	No
Number of 8-bit I/O ports	7	5
Auxiliary I/O Data/Address bus	Yes	None
Number of serial ports	6	4
Serial ports capable of SPI/clocked serial	4 (A, B, C, D)	2 (A, B)
Serial ports capable of SDLC/HDLC	2 (E, F)	None
Asynch serial ports with support for IrDA communications	6	None
Serial ports with support for SDLC/HDLC IrDA communications	2	None
Maximum asynchronous baud rate	clock speed/8	clock speed/32
Input capture unit	2	None