16. AC Timing Specifications

The Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V, and at temperatures from -40°C to +85°C with use possible use over the extended range -55°C to +105°C. For long life it is desirable not to exceed a die temperature of 125°C. Most users will operate the Rabbit at 3.3 V.

16.1 Memory Access Time

Required memory address and output enable access time for some important typical cases are given in the table below. It is assumed that the clock doubler is used, that the clock spreader is enabled in the normal mode, and that the address bus has 60 pF load. Values are given for the industrial temperature and voltage (+-10% in V) range at 3.3 V.

Table 16-1. Memory Requirements at 3.3 V, -40°C-+85°C, Adr Bus 60 pF

Clock Frequency (MHz)	Period (ns)	Clock Doubler Nominal Delay (ns)	Memory Address Access (ns)	Memory Output Enable Access (ns)
18.43	54	20	97	60
22.11	45	20	78	51
24.00	42	19	72	45
25.80	39	17	66	43
29.49	34	16	56	37
44.24	22.5	10	33.5	22

All important signals on the Rabbit 3000 are output synchronized with the internal clock. The internal clock is closely synchronized with the external clock (CLK) that may be optionally output from pin 2 of the TQFP package. The delay in signal output depends on the capactive load on the output lines. In the case of the address lines, which are critically important for establishing memory access time requirements, the capactive loading is usually in the range of 25-100 pF, and the load is due to the input capactance of the memory devices and PC trace capactance. Delays are expressed from the waveform midpoint in keeping with the convention used by memory manufacturers.

Figure 16-1 illustrates the parameters used to describe memory access time.

Figure 16-1. Parameters Used to Describe Memory Access Time

Table 16-2 lists the delays in gross memory access time for several values of VDD.

Table 16-2. Data and Clock Delays VDD ±10%, Temp, -40°C-+85°C (maximum)

VDD	Clock to Address Output Delay (ns)			Data Setup Time Delay (ns)	Spectrum Spreader Delay (ns)
	30 pF	60 pF	90 pF		Normal dbl/no dbl	Strong dbl/no dbl
3.3	6	8	11	1	3/4.5	4.5/9
2.7	7	10	13	1.5	3.5/5.5	5.5/11
2.5	8	11	15	1.5	4/6	6/12
1.8	18	24	33	3	8/12	11/22

When the spectrum spreader is enabled with the clock doubler, every other clock cycle is shortened (sometimes lengthened) by a maximum amount given in the table above. The shortening takes place by shortening the high part of the clock. If the doubler is not enabled, then every clock is shortened during the low part of the clock period. The maximum shortening for a pair of clocks combined is shown in the table.

Figure 16-2 and Figure 16-3 illustrate the memory and I/O read and write cycles. The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified.

Figure 16-2. Memory Read and Write Cycles

The following memory read time delays were measured.

Table 16-3. Memory Read Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Clock to address delay (Tadr)	6 ns	8 ns	11 ns
Clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Clock to memory read strobe delay (TOEx)	6 ns	8 ns	11 ns
Data setup time (Tsetup)	1 ns
Data hold time (Thold)	1 ns

The measurements were taken at the 50% points under the following conditions.

• T = -40°C to 85°C, V = 3.3 V

• Internal clock to nonloaded CLK pin delay # 1 ns @ 85°V/4.5 V

The following memory write time delays were measured.

Table 16-4. Memory Write Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Clock to address delay (Tadr)	6 ns	8 ns	11 ns
Clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Clock to memory write strobe delay (TWEx)	6 ns	8 ns	11 ns

The measurements were taken at the 50% points under the same conditions that the memory read delays were measured.

See Table 16-2 for delays at other voltages.

Figure 16-3. I/O Read and Write Cycles No Extra Wait States

The following I/O read time delays were measured.

Table 16-5. I/O Read Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Clock to address delay (Tadr)	6 ns	8 ns	11 ns
Clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Clock to I/O chip select delay (TIOCSx)	6 ns	8 ns	11 ns
Clock to I/O read strobe delay (TIORD)	6 ns	8 ns	11 ns
Clock to I/O buffer enable delay (TBUFEN)	6 ns	8 ns	11 ns
Data setup time (Tsetup)	1 ns
Data hold time (Thold)	1 ns

The measurements were taken at the 50% points under the following conditions.

• T = -40°C to 85°C, V = 3.3 V

• Internal clock to nonloaded CLK pin delay # 1 ns @ 85°V/4.5 V

The following I/O write time delays were measured.

Table 16-6. I/O Write Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Clock to address delay (Tadr)	6 ns	8 ns	11 ns
Clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Clock to I/O chip select delay (TIOCSx)	6 ns	8 ns	11 ns
Clock to I/O write strobe delay (TIOWR)	6 ns	8 ns	11 ns
Clock to I/O buffer enable delay (TBUFEN)	6 ns	8 ns	11 ns

The measurements were taken at the 50% points under the same conditions that the I/O read delays were measured.

I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified.

See Table 16-2 for delays at other voltages.

Figure 16-4 illustrates the sources that create memory access time delays.

Figure 16-4. Sources of Memory Access Time Delays

The gross memory access time is 2T, where T is the clock period. To calculate the actual memory access time, subtract the clock to address output time, the data in setup time, and the clock period shortening due to the clock spectrum spreader from 2T.

Example

• clock = 29.49 MHz,

• T = 34 ns,

• operating voltage is 3.3 V,

• bus loading is 60 pF,

• address to output time = 8 ns (see Table 16-2),

• data setup time = 1 ns,

• the spectrum spreader is on in normal mode, resulting in a loss of 3 ns.

The access time is given by

access time = 2T - (clock to address) - (data setup) - (spreader delay)
= 68 ns - 8 ns - 1 ns - 3 ns
= 56 ns

The required memory output enable access time is more complicated since it is affected by the clock doubler delays. The clock doubler setup register creates a nominal delay time ranging from 6 to 20 ns, resulting in a nominal clock low time ranging from 6 to 20 ns. The clock low time depends on internal delays, and is subject to variation arising from process variation, operating voltage and temperature. Minimum and maximum clock low times for various doubler settings are given in the formulas and in the graph below.

Max. delay @ 3.3 V = 6.1 + 1.21(n - 6) [n is the nominal delay, 6-20 ns)

Min. delay @ 3.3 V = 3.7 + 0.75(n - 6)

Max. delay @ 2.5 V = 7.6 + 1.67(n - 6)

Min. delay @ 2.5 V = 4.7 + 1.03(n - 6)

Max. delay @ 1.8 V = 12.2 + 2.7(n - 6)

Min. delay @ 1.8 V = 6.6 + 1.44(n - 6)

Figure 16-5. Clock Doubler Max-Min Clock Low Times

The following factors have to be taken into account when calculating the output enable access time required.

• The gross output enable access time is T + minimum clock low time (it is asusmed that the early output enable option is enabled) This is reduced by the spectrum spreader loss, the time from clock to output for the output enable signal, the data setup time, and a correction for the asymmetery of the original oscillator clock.

Example

• Clock = 29.49 MHz,

• T = 34 ns,

• operating voltage is 3.3 V,

• the clock doubler has a nominal delay of 16 ns, resulting in a minimum clock low time of 12.8 ns,

• the spectrum spreader is on in normal mode, resulting in a loss of 3 ns,

• clock to output enable is 5 ns (assuming 20 pF load),

• the clock asymmetery is 52-48, resulting in a loss of 4% of the clock period, or 1.4 ns.

The output enable access time is given by

access time
= T + (min. clock low) - (clock to output enable) - (spreader delay) - (assymmetry delay)
- (data setup time)
= 34 ns + 12.8 ns - 5 ns - 3 ns - 1.36 ns - 1 ns
= 36.5 ns

16.2 Further Discussion of Bus and Clock Timing

The clock doubler is normally used, except in situations where low-frequency systems are specifically being used. The clock doubler works by oring the clock with a delayed version of itself. The nominal delay varies from 6 to 20 ns, and is settable under program control. Any assymetry in the oscillator waveform before it is doubled will result in alternate clocks having slightly different periods. Using the suggested oscillator circuit, the asymmetry is no worse than 52%-48%. This results in a given clock being shortened by the ratio 50/52, or 4%. Memory access time is not affected because memory bus cycle is 2 clocks long and includes both a long and a short clock, resulting in no net change due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly.

When the clock spectrum spreader is enabled, clock periods are shortened by a small amount depending on whether the "normal" or the "strong" spreader setting is used, and depending on the operating voltage. If the clock doubler is used, the spectrum spreader affects every other cycle and reduces the clock high time. If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. Of course, the spectrum spreader also lengthens clock cycles, but only the worst case shortening is relevant for calculating worst case access times. The numbers given for clock shortening with the doubler disabled are the combined shortening for 2 consecutive clock cycles, worst case.

In computing memory requirements, the important considerations are address access time, output enable access time, and minimum write pulse required. Increasing the clock doubler delay increases the output enable time, but decreases memory write pulse width. The early write pulse option can be used to ensure a long-enough write pulse, but then it must be ensured that the write pulse does not begin before the address lines have stablized.

Figure 16-6.

16.3 Power and Current Consumption

With the Rabbit 3000 it is possible to design systems that perform their task with very low power consumption. Unlike competitive processors, the Rabbit 3000 has short chip select features designed to minimize power consumption by external memories, which can easily become the dominent power consumers at low clock frequencies if not well handled.

The preferred configuration for a Rabbit-based system is to use an external crystal or resonator that has a frequency ½ of the maximum internal clock frequency. The oscillator frequency can be doubled or divided by 2, 4, 6, or 8, giving a variety of operating speeds from the same crystal frequency. In addition, the 32.768 kHz oscillator the drives the battery-backable clock can be used as the main processor clock and, to save the substantial power consumed by the fast oscillator, the fast oscillator can be turned off. This scenario is called the sleepy mode with a clock speed in the range of 2 kHz to 32 kHz, and with an operating system current consumption in the range of 10 to 120 µA depending on frequency and voltage.

Up to an operating speed of 29.5 MHz, a SST39LF512020 256K × 8, 45 ns access time flash memory combined with any of several 55 ns low-power SRAMs is assumed for calculating the current consumption estimates below.

A crystal frequency of 3.6864 MHz is a good choice for a low-power system consuming between 2 and 18 mA at 3.3 V as the clock frequency is throttled between 0.46 MHz and 7.37 MHz. The required memory access time is about 250 ns, however, a faster memory may result in less power since a short chip select cycle can then be used.

A crystal frequency of 11.0592 MHz is a good choice for a medium-power system consuming between 5 and 50 mA at 3.3 V as the clock frequency is throttled between 1.4 MHz and 22 MHz. The required memory access time is 70 ns.

A crystal frequency of 14.7456 MHz is a good choice for a faster medium-power system consuming between 6 and 65 mA at 3.3 V as the clock frequency is throttled between 1.8 and 29.5 MHz. The required memory access time is 55 ns.

A maximum-speed system that will require fast RAM for program and data can be constructed using a 25.8048 MHz crystal. This system will consume between 12 and 112 mA at 3.3V as the clock speed is throttled between 3 and 51.6 MHz. The required memory access time is about 20 ns.

Typical system current consumptions are shown in the graphs below. These are for the processor and oscillator only, and do not include current consumed by memory and other devices. It is assumed that that approximately 30 pF is connected to each address line, particularly A0 and A1, which account for three quarters of the charging current due to the address lines.

Figure 16-7. Rabbit 3000 System Current vs. Frequency at 3.3 V

Figure 16-8. Rabbit 3000 System Current vs. Frequency at 3.3 V

Lowering the operating voltage will greatly reduce current consumption and power. Dropping to 2.7 V from 3.3 V will result in 70% current consumption and 60% of the power. Further dropping to 1.8 V will reduce current to 40% and power to 20% compared to 3.3 V. Naturally this complicates the selection of memories, especially at 1.8 V.

It is important to know that the lowest speed crystal will not always give the lowest power consumption because when the crystal is divided internally the short chip select option can be used to reduce the chip select duty cycle of the flash memory or fast RAM, greatly reducing the static current consumption associated with some memories.

In sleepy mode, power consumption consists of the processor core, the external recommended external tiny logic 32 kHz oscillator, and the memory. The oscillator consumes 17 µA at 3.3 V, and this drops rapidly to about 2 µA at 1.8 V. The processor core consumes between 3 and 50 µA at 3.3 V as the frequency is throttled from 2 kHz to 32 kHz, and about 40% as much at 1.8 V. If the flash memory specified above is used for memory and a self-timed 106 ns chip select is used, then the memory will consume 22 µA at 32 MHz and 1.4 µA at 2 kHz.

In addition to these items, a low-power reset controller may consume about 8 µA and CMOS leakage may consume several µA, increasing with higher temperatures. The graph below shows current consumption including the tiny logic core, but not including memory or the reset controller.

Figure 16-9. Sleepy Mode Current Consumption

16.4 Current Consumption Mechanisms

The following mechanisms are important for the current consumption of the Rabbit 3000 while it is operating.

1. A current proportional to voltage and clock frequency that results from the charging of internal and external capacitances. At 3.3 V (see 2 below) approximately 57% of the current is due to charging and 43% to crossover current.

2. A current proportional to clock frequency and to Vc= V(0.5× V - 0.7). This is the crossover current that results from a brief short circuit when both the P and N transistors of a CMOS buffer are turned on at the same time. This component drops as the voltage drops relative to the other component, and becomes negligible at 1.4 V.

3. The current consumed by the built-in main oscillator when turned on. This current is proportional to Vc above, and is equal to 1 mA at 3.3 V.

4. The current drawn by the logic that is driven at the oscillator (crystal frequency). This is considered distinctly because it varies with the crystal frequency, but is not reduced when the clock frequency is divided. This current becomes zero if the main oscillator is turned off. This current is 2.5 mA at 3.3 V when the crystal frequency is 14.7 MHz. This current is divided between capacitive and crossover components in the same manner as the currents in (1) and (2) above.

All of the above components can be combined in the following formula:

Itotal = 0.32× V× f + 0.23× Vc× f + 0.30× Vc + 0.029× V× fc + 0.025× Vc× fc

where Vc = V× (0.5× V - 0.7), fc = frequency of crystal oscillator, and f = clock frequency in MHz

16.5 Sleepy Mode Current Consumption

In sleepy mode the unit operates from the 32.768 kHz clock, which may be divided down to as slow as 2.048 kHz. The current consumption is given by:

Itotal = 0.32× V× f + 0.23× Vc× f + 5× Vc

where f is in kHz, V is the operating voltage, and Vc = V× (V/2 - 0.7).

Leakage, the standby current of the reset generator, the current consumption of the oscillator and the real-time clock, and the current consumption of memories must be added to the sleepy mode current consumption. Generally the self-timed chip select mode is used to reduce memory current consumption.

16.6 Memory Current Consumption

Since there are many different memories available, let's look at an example using one of the recommended flash and SRAM memories.

Flash memory--SST part SST39LF512020, 256K × 8, 45 ns access time. Standby current: nil.

• Static Current (chip select low): 3.5 mA @ 3.3 V

• Dynamic Current: 7 mA at 14.7 MHz bus speed and 3.3 V

The total current is 10 mA at a clock speed of 29.49 MHz or a bus speed of 5 MHz.

The static part of the current is computed using

0.35× (chip select duty cycle).

The dynamic part is computed using

0.5× f in mA,

where f is the bus speed in MHz.

At 0.46 MHz (3.68 MHz/8), and using a short chip select, the duty cycle is about 10%, giving a static current of about 0.35 mA. The dynamic current is 0.25 mA, for a total current of 0.6 mA. Added to the approximately 2.5 mA operating current gives a total current of 3.1 mA at 0.46 MHz.

In sleepy mode with a self-timed chip select of 106 ns and a clock speed of 32 kHz, the duty cycle will be 0.106/66 = 1/600, and the static current will be 3.5/600= 6 µA. If the clock is divided down by a factor of 2, then the static current is reduced to 3 µA. The dynamic current will be 16 µA at 32 kHz (1000× 0.5× f) and 8 µA at 16 kHz.

16.7 Battery-Backed Clock Current Consumption

When using the suggested tiny logic oscillator, the oscillator and clock consume current as shown in Figure 16-10 below. Normally a resistor is placed in the battery circuit to limit the current to about 3 µA, which results in a voltage setpoint of about 1.7 V. When operating at 3.3 V in sleepy mode, the current of the oscillator and the real-time clock--about 12 µA--must be added.

Using the suggested tiny logic oscillator circuit, the external 32.768 kHz oscillator consumes the following current in µA, where V is the operating voltage.

Iosc = 0.35× V2 + 0.31× V

Generally the oscillator will not start unless the voltage is about 1.4 V. However, the oscillator will continue to run until the voltage drops to about 0.8 V. If the oscillator stops, the current draw is very much lower than when it is running. Below about 1.4 V most of the current draw is used to charge and discharge the capactive load.

The current consumed by the battery-backed portion of the Rabbit 3000, which is driven by the 32.768 kHz oscillator, is given by

Irab = 0.91× V2 - 1.04× V (V > 1.14 V)

where Irab is in µA. For V <1.14 V, the current is negligible.

Figure 16-10. Current Consumption--Real-Time Clock and 32 kHz Oscillator Circuit

16.8 Reduced-Power External Main Oscillator

The circuit in Figure 16-11 can be used to generate the main clock using less power than with the built-in oscillator buffer. The power consumption is less because of the current-limiting resistors that cannot be used with the built-in buffer. The 2.2 kW series resistor must be reduced as the clock frequency increases, as must be the current-limiting resistors.

Figure 16-11. Reduced-Power External Main Oscillator

Table 16-7 lists results for the reduced-power external oscillator with no current-limiting resistors.

Table 16-7. Current Draw Using Reduced-Power External Oscillator
(0 W current-limiting resistors)

Voltage (V)	Current (incl built-in buffer) (mA)
3.3	0.635
2.5	0.380
1.8	0.252

Design Recommendations

• Add current-limiting resistors to reduce current without inhibiting oscillator start-up

• Increase the 1 MW resistor to improve gain

• Minimize loop area to reduce EMI