ADC A,(HL)
ADC A,(IX+d)
ADC A,(IY+d)
|
|
|
| 8E |
ADC A,(HL) |
5 (2,1,2) |
A= A + (HL) + CF |
| DD 8E d |
ADC A,(IX+d) |
9 (2,2,2,1,2) |
A= A + (IX+d) + CF |
| FD 8E d |
ADC A,(IY+d) |
9 (2,2,2,1,2) |
A= A + (IY+d) + CF |
Description
The data in the Accumulator is summed with the Carry Flag and with the data in memory whose location is:
- held in word register HL, or
- the sum of the data in index register IX and a displacement value d, or
- the sum of the data in index register IY and a displacement value d.
The result is then stored in the Accumulator.
|
| CE n |
ADC A,n |
4 (2,2) |
A = A + n + CF |
Description
The 8-bit constant n is summed with the Carry Flag and with the data in the Accumulator. The sum is then
stored in the Accumulator.
|
| ---- |
ADC A,r |
2 |
A = A + r + CF |
| 8F |
ADC A,A |
2 |
A = A + A + CF |
| 88 |
ADC A,B |
2 |
A = A + B + CF |
| 89 |
ADC A,C |
2 |
A = A + C + CF |
| 8A |
ADC A,D |
2 |
A = A + D + CF |
| 8B |
ADC A,E |
2 |
A = A + E + CF |
| 8C |
ADC A,H |
2 |
A = A + H + CF |
| 8D |
ADC A,L |
2 |
A = A + L + CF |
Description
The data in the Accumulator is summed with the Carry Flag, CF, and with the data in register r (any of the
registers A, B, C, D, E, H, or L). The result is stored in the Accumulator.
|
| ---- |
ADC HL,ss |
4 (2,2) |
HL = HL + ss + CF |
| ED 4A |
ADC HL,BC |
4 (2,2) |
HL = HL + BC + CF |
| ED 5A |
ADC HL,DE |
4 (2,2) |
HL = HL + DE + CF |
| ED 6A |
ADC HL,HL |
4 (2,2) |
HL = HL + HL + CF |
| ED 7A |
ADC HL,SP |
4 (2,2) |
HL = HL + SP + CF |
Description
The data in the register pair HL is summed with the Carry Flag and with the data in word register ss (any of
the word registers BC, DE, HL, or SP). The result is stored in HL.
ADD A,(HL)
ADD A,(IX+d)
ADD A,(IY+d)
|
|
|
| 86 |
ADD A,(HL) |
5 (2,1,2) |
A = A + (HL) |
| DD 86 d |
ADD A,(IX+d) |
9 (2,2,2,1,2) |
A = A + (IX+d) |
| FD 86 d |
ADD A,(IY+d) |
9 (2,2,2,1,2) |
A = A + (IY+d) |
Description
The data in the Accumulator is summed with the data in the memory location whose address is:
- held in word register HL, or
- the sum of the data in index register IX and a displacement value d, or
- the sum of the data in index register IY and a displacement value d.
The result is stored in the Accumulator.
|
| C6 n |
ADD A,n |
4 (2,2) |
A = A + n |
Description
The data in the Accumulator is summed with the 8-bit constant n. The result is stored in the Accumulator.
|
| ---- |
ADD A,r |
2 |
A = A + r |
| 87 |
ADD A,A |
2 |
A = A + A |
| 80 |
ADD A,B |
2 |
A = A + B |
| 81 |
ADD A,C |
2 |
A = A + C |
| 82 |
ADD A,D |
2 |
A = A + D |
| 83 |
ADD A,E |
2 |
A = A + E |
| 84 |
ADD A,H |
2 |
A = A + H |
| 85 |
ADD A,L |
2 |
A = A + L |
Description
The data in the Accumulator is summed with the data in register r (any of the registers A, B, C, D, E, H, or L).
The result is stored in the Accumulator.
|
----
09
19
29
39 |
ADD HL,ss
ADD HL,BC
ADD HL,DE
ADD HL,HL
ADD HL,SP |
2
2
2
2
2 |
HL = HL + ss
HL = HL + BC
HL = HL + DE
HL = HL + HL
HL = HL + SP |
Description
The data in the word register HL is summed with the data in the word register ss (any of the word registers
BC, DE, HL, or SP). The result is stored in HL.
|
----
DD 09
DD 19
DD 29
DD 39 |
ADD IX,xx
ADD IX,BC
ADD IX,DE
ADD IX,IX
ADD IX,SP |
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2) |
IX = IX + xx
IX = IX + BC
IX = IX + DE
IX = IX + IX
IX = IX + SP |
----
FD 09
FD 19
FD 29
FD 39 |
ADD IY,yy
ADD IY,BC
ADD IY,DE
ADD IY,IY
ADD IY,SP |
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2) |
IY = IY + yy
IY = IY + BC
IY = IY + DE
IY = IY + IY
IY = IY + SP |
Description
The data in index register IX is summed with the word register xx (any of the word registers BC, DE, IX, or
SP) and the result is stored in IX.
The data in index register IY is summed with the word register yy (any of the word registers BC, DE, IY, or
SP). The result is stored in IY.
|
| 27 d |
ADD SP,d |
4 (2,2) |
SP = SP + d |
Description
The data in the Stack Pointer register is summed with the 7-bit signed displacement d, and then stored in SP.
This instruction is implemented for the Rabbit and is not available for the Z180.
|
| 76 |
ALTD |
2 |
[Sets alternate register destination for following instruction.] |
Description
This is an instruction prefix. Causes the instruction immediately following to affect the alternate flags, or use
the alternate registers for the destination of the data, or both. For some instructions ALTD causes special
alternate register uses, unique to that instruction. This instruction is implemented for the Rabbit and is not
available for the Z180
Example
The instruction
ALTD ADD HL,DE
would add the data in word register DE to the data in word register HL and store the result in the alternate
word register HL'.
The instructions
ALTD LD DE,BC
and
LD DE',BC
both load the data in word register BC into the alternate word register DE'.
AND (HL)
AND (IX+d)
AND (IY+d)
|
|
|
| A6 |
AND (HL) |
5 (2,1,2) |
A = A & (HL) |
| DD A6 d |
AND (IX+d) |
9 (2,2,2,1,2) |
A = A & (IX+d) |
| FD A6 d |
AND (IY+d) |
9 (2,2,2,1,2) |
A = A & (IY+d) |
Description
Performs a logical AND operation between the byte in the Accumulator and the byte whose address is:
- in word register HL, or
- the sum of the data in index register IX and a displacement value d, or
- the sum of the data in index register IY and a displacement value d.
The relative bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes
are compared, etc.) and the associated bit in the result byte is set only if both the compared bits are set. The
result is stored in the Accumulator.
Example
If the byte in the Accumulator contains the bits 1011 1100 and the byte at memory location HL contains the
bits 1101 0101, then the execution of the instruction:
AND (HL)
would result in the byte in the Accumulator becoming 1001 0100.
|
| DC |
AND HL,DE |
2 |
HL = HL& DE |
Description
Performs a logical AND operation between the word in word register HL and the word in word register DE.
The relative bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes
are compared, etc.) and the associated bit in the result byte is set only if both the compared bits are set. The
result is stored in HL. This instruction is implemented for the Rabbit and is not available for the Z180.
|
| DD DC |
AND IX,DE |
4 (2,2) |
IX = IX & DE |
| FD DC |
AND IY,DE |
4 (2,2) |
IY = IY & DE |
Description
-
AND IX,DE performs a logical AND operation between the word in index register IX and the word in word register DE. The result is stored in IX.
-
AND IY,DE performs a logical AND operation between the word in index register IY and the word in word register DE. The result is stored in IY.
The relative bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes
are compared, etc.) and the associated bit in the result byte is set only if both the compared bits are set. These
instructions are implemented for the Rabbit and are not available for the Z180.
|
| E6 n |
AND n |
4 (2,2) |
A = A & n |
Description
Performs a logical AND operation between the byte in the Accumulator and the 8-bit constant n. The relative
bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes are compared,
etc.) and the associated bit in the result byte is set only if both the compared bits are set. The result is stored in
the Accumulator.
|
----
A7
A0
A1
A2
A3
A4
A5 |
AND r
AND A
AND B
AND C
AND D
AND E
AND H
AND L |
2
2
2
2
2
2
2
2 |
A = A & r
A = A & A
A = A & B
A = A & C
A = A & D
A = A & E
A = A & H
A = A & L |
Description
Performs a logical AND operation between the byte in the Accumulator and the byte in the register r (any of
the registers A, B, C, D, E, H, or L). The relative bits of each byte are compared (i.e., the bit 1 of both bytes
are compared, the bit 2 of both bytes are compared, etc.) and the associated bit in the result byte is set only if
both the compared bits are set. The result is stored in the Accumulator.
BIT b,(HL)
BIT b,(IX+d)
BIT b,(IY+d)
|
|
|
----
CB 46
CB 4E
CB 56
CB 5E
CB 66
CB 6E
CB 76
CB 7E |
BIT b,(HL)
BIT 0,(HL)
BIT 1,(HL)
BIT 2,(HL)
BIT 3,(HL)
BIT 4,(HL)
BIT 5,(HL)
BIT 6,(HL)
BIT 7,(HL) |
7 (2,2,1,2)
7 (2,2,1,2)
7 (2,2,1,2)
7 (2,2,1,2)
7 (2,2,1,2)
7 (2,2,1,2)
7 (2,2,1,2)
7 (2,2,1,2)
7 (2,2,1,2) |
(HL) & bit
(HL) & bit 0
(HL) & bit 1
(HL) & bit 2
(HL) & bit 3
(HL) & bit 4
(HL) & bit 5
(HL) & bit 6
(HL) & bit 7 |
----
DD CB d 46
DD CB d 4E
DD CB d 56
DD CB d 5E
DD CB d 66
DD CB d 6E
DD CB d 76
DD CB d 7E |
BIT b,(IX+d)
BIT 0,(IX+d)
BIT 1,(IX+d)
BIT 2,(IX+d)
BIT 3,(IX+d)
BIT 4,(IX+d)
BIT 5,(IX+d)
BIT 6,(IX+d)
BIT 7,(IX+d) |
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2) |
(IX+d) & bit
(IX+d) & bit 0
(IX+d) & bit 1
(IX+d) & bit 2
(IX+d) & bit 3
(IX+d) & bit 4
(IX+d) & bit 5
(IX+d) & bit 6
(IX+d) & bit 7 |
----
FD CB d 46
FD CB d 4E
FD CB d 56
FD CB d 5E
FD CB d 66
FD CB d 6E
FD CB d 76
FD CB d 7E |
BIT b,(IY+d)
BIT 0,(IY+d)
BIT 1,(IY+d)
BIT 2,(IY+d)
BIT 3,(IY+d)
BIT 4,(IY+d)
BIT 5,(IY+d)
BIT 6,(IY+d)
BIT 7,(IY+d) |
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2)
10 (2,2,2,2,2) |
(IY+d) & bit
(IY+d) & bit 0
(IY+d) & bit 1
(IY+d) & bit 2
(IY+d) & bit 3
(IY+d) & bit 4
(IY+d) & bit 5
(IY+d) & bit 6
(IY+d) & bit 7 |
Description
Tests the bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the byte whose address is:
- contained in the register pair HL, or
- the sum of data in index register IX plus a displacement value d, or
- the data in index register IY plus a displacement value d.
The Zero Flag, Z, is set if the tested bit is 0, reset the bit is 1.
BIT b,(HL) is a privileged instruction.
|
| b,r |
A |
B |
C |
D |
E |
H |
L |
|
|
|
| CB (0) |
47 |
40 |
41 |
42 |
43 |
44 |
45 |
|
| CB (1) |
4F |
48 |
49 |
4A |
4B |
4C |
4D |
| CB (2) |
57 |
50 |
51 |
52 |
53 |
54 |
55 |
| CB (3) |
5F |
58 |
59 |
5A |
5B |
5C |
5D |
| CB (4) |
67 |
60 |
61 |
62 |
63 |
64 |
65 |
| CB (5) |
6F |
68 |
69 |
6A |
6B |
6C |
6D |
| CB (6) |
77 |
70 |
71 |
72 |
73 |
74 |
75 |
| CB (7) |
7F |
78 |
79 |
7A |
7B |
7C |
7D |
Description
Tests the bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the byte in the register r (any of the registers A, B, C,
D, E, H, or L).
The Zero Flag, Z, is set if the tested bit is 0, reset if the bit is 1.
|
| CC |
BOOL HL |
2 |
If (HL != 0) HL = 1 |
Description
If the data in word register HL does not equal zero, then it is set to 1. This instruction is implemented for the
Rabbit and is not available for the Z180.
|
| DD CC |
BOOL IX |
4 (2,2) |
If (IX != 0) IX = 1 |
| FD CC |
BOOL IY |
4 (2,2) |
If (IY != 0) IY = 1 |
Description
If the data in index register IX or IY does not equal zero, then that register is set to 1. These instructions are
implemented for the Rabbit and are not available for the Z180.
|
| CD n m |
CALL mn |
12 (2,2,2,3,3) |
(SP - 1) = PC(high);
(SP - 2) = PC(low);
PC = mn; SP = SP - 2 |
Description
This instruction is used to call a subroutine. First the data in the Program Counter is pushed onto the stack.
The high-order byte of the PC is pushed first, then the low-order byte. The program counter is then loaded
with mn,16-bit address of the first instruction of the subroutine. The Stack Pointer is updated to reflect the two
bytes pushed onto the stack.
The Dynamic C assembler recognizes CALL label, where mn is coded as a label.
Description
The Carry Flag is inverted: If it is set, it becomes cleared. If it is not set, it becomes set.
CP (HL)
CP (IX+d)
CP (IY+d)
|
|
|
| BE |
CP (HL) |
5 (2,1,2) |
A - (HL) |
| DD BE d |
CP (IX + d) |
9 (2,2,2,1,2) |
A - (IX + d) |
| FE BE d |
CP (IY + d) |
9 (2,2,2,1,2) |
A - (IY + d) |
Description
Compares the data in the Accumulator with the data whose address is (a) contained in word register HL, (b)
the sum of the data in index register IX plus a displacement value d, or (c) the sum of the data in index register
IY plus a displacement value d.
These compares are accomplished by subtracting the appropriate data ((HL), (IX+d), or (IY+d)) from the
Accumulator. If the value of the data in the Accumulator is less than the value of the data compared, then the
Sign Flag and the Carry Flag are set. If they are equal, the Zero Flag is set. If the data is greater than the data
in the Accumulator, then the Sign, Carry, and Zero Flags are reset. This operation does not affect the data in
the Accumulator.
Description
Compares the data in the Accumulator with an 8-bit constant n. This compare is accomplished by subtracting
n from the Accumulator. If the value of the data in the Accumulator is less than the value of n, then the Sign
Flag and the Carry Flag are set. If they are equal, the Zero Flag is set. If n is greater than the data in the Accumulator,
then the Sign, Carry, and Zero Flags are reset. This operation does not affect the data in the Accumulator.
|
----
BF
B8
B9
BA
BB
BC
BD |
CP r
CP A
CP B
CP C
CP D
CP E
CP H
CP L |
2
2
2
2
2
2
2
2 |
A - r
A - A
A - B
A - C
A - D
A - E
A - H
A - L |
Description
Compares the data in Accumulator with the data in register r (any of the registers A, B, C, D, E, H, or L). This
compare is accomplished by subtracting the appropriate data (r) from the Accumulator. If the value of the
data in the Accumulator is less than the value of the data compared, then the Sign Flag and the Carry Flag are
set. If they are equal, the Zero Flag is set. If the data is greater than the data in the Accumulator, then the Sign,
Carry, and Zero Flags are reset. This operation does not affect the data in the Accumulator
Description
The data in the Accumulator is inverted (one's complement).
Example
If the data in the Accumulator is 1100 0101, after the instruction CPL the Accumulator will contain
0011 1010.
DEC (HL)
DEC (IX+d)
DEC (IY+d)
|
|
|
| 35 |
DEC (HL) |
8 (2,1,2,3) |
(HL) = (HL) - 1 |
| DD 35 d |
DEC (IX+D) |
12 (2,2,2,1,2,3) |
(IX + d) = (IX + d) - 1 |
| FD 35 d |
DEC (IY+D) |
12 (2,2,2,1,2,3) |
(IY + d) = (IY + d) - 1 |
Description
Decrements the byte whose address is:
- in word register HL, or
- the data in index register IX plus a displacement value d, or
- the data in index register IY plus a displacement value d.
|
| DD 2B |
DEC IX |
4 (2,2) |
IX = IX - 1 |
| FD 2B |
DEC IY |
4(2,2) |
IY = IY - 1 |
Description
Decrements the data in index register IX or IY.
|
---- 3D
05
0D
15
1D
25
2D |
DEC r
DEC A
DEC B
DEC C
DEC D
DEC E
DEC H
DEC L |
2
2
2
2
2
2
2
2 |
r = r - 1
A = A - 1
B = B - 1
C = C - 1
D = D - 1
E = E - 1
H = H - 1
L = L - 1 |
Description
Decrements the data in the register r (any of the registers A, B, C, D, E, H, or L).
|
----
0D
1D
2D
3D |
DEC ss
DEC BC
DEC DE
DEC HL
DEC SP |
2
2
2
2
2 |
ss = ss - 1
BC = BC - 1
DE = DE - 1
HL = HL - 1
SP = SP - 1 |
Description
Decrements the data in word register ss (any of the word registers BC, DE, HL, or SP).
|
| 10 e-2 |
DJNZ e |
5 (2,2,1) |
B = B-1; if {B != 0} PC = PC + e |
Description
This instruction's mnemonic stands for Decrement and Jump if Not Zero. It decrements the data in register B
then, if the data in B does not equal 0, it adds the 8-bit signed constant e to the Program Counter.
Two is subtracted from the value e so the instruction jumps from the current instruction and not the following
instruction.
|
| ED 54 |
EX (SP),HL |
15 (2,2,1,2,2,3,3) |
H <-> (SP+1); L <-> (SP) |
Description
Exchanges the byte in the register H with the data whose address is the data in the Stack Pointer register
plus 1; and exchanges the byte in the register L with the data whose address is the data in the Stack Pointer .
This instruction has been modified from the Z180 instruction.
|
| DD E3 |
EX (SP),IX |
15 (2,2,1,2,2,3,3) |
IX(high) <-> (SP+1);
IX(low) <-> (SP) |
| FD E3 |
EX (SP),IY |
15 (2,2,1,2,2,3,3) |
IY(high) <-> (SP+1);
IY(low) <-> (SP) |
Description
-
EX (SP),IX exchanges the high order byte of index register IX with the data whose address is 1 plus the data in the Stack Pointer register, and exchanges the low order byte of index register IX with the data whose address is the data in the Stack Pointer register, SP.
-
EX (SP),IY exchanges the high order byte of index register IY with the data whose address is 1 plus the data in the Stack Pointer register, and exchanges the low order byte of index register IY with the data whose address is the data in the Stack Pointer register.
|
| 08 |
EX AF,AF' |
2 |
AF <-> AF' |
Description
Exchanges the data in word register AF with the data in the alternate word register AF'.
|
| EB |
EX DE,HL |
2 |
if (!ALTD) then DE <-> HL else DE <-> HL' |
| E3 |
EX DE',HL |
2 |
if (!ALTD) then DE' <-> HL else DE' <-> HL' |
Description
-
EX DE,HL exchanges the data in word register DE with the data in word register HL. If the ALTD instruction is present then the data in DE is exchanged with the data in the alternate word register HL'. This instruction is implemented for the Rabbit and is not available for the Z180.
-
EX DE',HL exchanges the data in the alternate word register DE' with the data in word register HL. If the ALTD instruction is present then the data in DE' is exchanged with the data in the alternate word register HL'.
The Dynamic C assembler recognizes the following instructions, which are based on a combination of ALTD
and the above exchange operations:
-
EX DE',HL' ; equivalent to ALTD EX DE',HL
-
EX DE,HL' ; equivalent to ALTD EX DE',HL'
|
| D9 |
EXX |
2 |
BC <-> BC'; DE <-> DE'; HL <-> HL' |
Description
Exchanges the data in word registers BC, DE, and HL, with the data in their respective alternate word registers
BC', DE', and HL'.
INC (HL)
INC (IX+d)
INC (IY+d)
|
|
|
| 34 |
INC (HL) |
8 (2,1,2,3) |
(HL) = (HL) + 1 |
| DD 34 d |
INC (IX+d) |
12 (2,2,2,1,2,3) |
(IX + d) = (IX + d) + 1 |
| FD 34 d |
INC (IY+d) |
12 (2,2,2,1,2,3) |
(IY + d) = (IY + d) + 1 |
Description
Increments the byte whose address is:
- held in word register HL, or
- the sum of the data in index register IX and a displacement value d, or
- the sum of the data in index register IY and a displacement value d.
|
| DD 23 |
INC IX |
4 (2,2) |
IX = IX + 1 |
| FD 23 |
INC IY |
4 (2,2) |
IY = IY + 1 |
Description
-
INC IX increments the data in index register IX.
-
INC IY increments the data in index register IY.
|
----
3C
04
0C
14
1C
24
2C |
INC r
INC A
INC B
INC C
INC D
INC E
INC H
INC L |
2
2
2
2
2
2
2
2 |
r = r + 1
A = A + 1
B = B + 1
C = C + 1
D = D + 1
E = E + 1
H = H + 1
L = L + 1 |
Description
Increments the data in the register r (any of the registers A, B, C, D, E, H, or L).
|
----
03
13
23
33 |
INC ss
INC BC
INC DE
INC HL
INC SP |
2
2
2
2
2 |
ss = ss + 1
BC = BC + 1
DE = DE + 1
HL = HL + 1
SP = SP + 1 |
Description
Increments the data in word register ss (any of the word registers BC, DE, HL, or SP).
|
| DD |
IOE |
2 |
I/O external prefix |
| D3 |
IOI |
2 |
I/O internal prefix |
Description
These instructions are implemented for the Rabbit and are not available for the Z180.
-
IOI: The IOI prefix allows the use of existing memory access instructions as internal I/O instructions. When prefixed, a 16-bit memory instruction accesses the I/O space at the address specified by the lower byte of the 16-bit address. With IOI, the upper byte of a 16-bit address is ignored since internal I/O peripherals are mapped within the first 256-bytes of the I/O address space. Writes to internal I/O registers require two clocks rather than the three required for memory write operations.
-
IOE: The IOE prefix allows the use of existing memory access instructions as external I/O instructions. Unlike internal I/O peripherals, external I/O devices can be mapped within 8K of the available 64K address space. Therefore, prefixed 16-bit memory access instructions can be used more appropriately for external I/O operations. By default, writes are inhibited for external I/O operations and fifteen wait states are added for I/O accesses.
WARNING: If an I/O prefixed instruction is immediately followed by one of these 12 special one byte
memory access instructions, a bug in the Rabbit 2000 causes I/O access to occur instead of memory access:
ADC A,(HL)
ADD A,(HL)
AND (HL) |
CP (HL)
OR (HL)
SBC A,(HL) |
SUB (HL)
XOR (HL)
DEC (HL) |
INC (HL)
LD r,(HL)
LD (HL),r |
This bug can be avoided by putting a NOP instruction between an I/O instruction and any of the aforementioned
instructions. Dynamic C versions 6.57 and later will automatically compensate for the bug. And the
Rabbit 3000 eliminated it.
Examples
The following instruction loads the contents of the Accumulator into the internal I/O register at address location
030h:
IOI LD (030h), A
These next instructions read a word from external I/O address 0A002:
LD IX, 0A000h
IOE LD HL, (IX+2)
IPSET 0
IPSET 1
IPSET 2
IPSET 3
|
|
|
| ED 46 |
IPSET 0 |
4 (2,2) |
IP = {IP[5:0], 00} |
| ED 56 |
IPSET 1 |
4 (2,2) |
IP = {IP[5:0], 01} |
| ED 4E |
IPSET 2 |
4 (2,2) |
IP = {IP[5:0], 10} |
| ED 5E |
IPSET 3 |
4 (2,2) |
IP = {IP[5:0], 11} |
Description
The Interrupt Priority Register, IP is an 8-bit register that forms a stack of the current priority and the other
previous 3 priorities. IPSET 0 forms the lowest priority; IPSET 3 forms the highest priority. These instructions
are privileged. They are implemented for the Rabbit and are not available for the Z180.
-
IPSET 0: The IPSET 0 instruction shifts the contents of the register holding the previous priorities 2-bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 00.
-
IPSET 1: The IPSET 1 instruction first shifts the contents of the register holding the previous priorities 2-bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 01.
-
IPSET 2: The IPSET 2 instruction shifts the contents of the register holding the previous priorities 2-bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 10.
-
IPSET 3: The IPSET 3 instruction shifts the contents of the register holding the previous priorities 2-bits to the left, then sets the Interrupt Priority Register (bits 0 and 1) to 11.
|
|
|
|
All interrupts, priority 1,2 and 3 take place after execution of current non privileged instruction. |
|
Only interrupts of priority 2 and 3 take place after execution of current non privileged
instruction. |
|
Only interrupts of priority 3 take place after
execution of current non privileged instruction. |
|
All interrupts are suppressed
(except the RST instruction). |
|
| ED 5D |
IPRES |
4 (2,2) |
IP = {IP[1:0], IP[7:2]} |
Description
The IPRES instruction rotates the contents of the Interrupt Priority Register 2-bits to the right, replacing the
current priority with the previous priority. It is impossible to interrupt during the execution of this instruction.
This instruction is privileged. It is implemented for the Rabbit and is not available for the Z180.
Example
If the Interrupt Priority register contains 00000110, the execution of the instruction
IPRES
would cause the Interrupt Priority register to contain 10000001.
JP (HL)
JP (IX)
JP (IY)
JP mn
|
|
|
| E9 |
JP (HL) |
4 (2,2) |
PC = HL |
| DD E9 |
JP (IX) |
6 (2,2,2) |
PC = IX |
| FD E9 |
JP (IY) |
6 (2,2,2) |
PC = IY |
| C3 n m |
JP mn |
7 (2,2,2,1) |
PC = mn |
Description
-
JP (HL): The data in HL is loaded into the Program Counter. Thus the address of the next instruction fetched is the data in HL.
-
JP (IX): The data in index register IX is loaded into the Program Counter. Thus the address of the next instruction fetched is the data in IX.
-
JP (IY): The data in index register IY is loaded into the Program Counter. Thus the address of the next instruction fetched is the data in IY.
-
JP mn: The 16-bit constant mn is loaded into the Program Counter. Thus the address of the next instruction fetched is mn. This instruction recognizes labels when used in the Dynamic C assembler.
|
----
C2 n m
CA n m
D2 n m
DA n m
E2 n m
EA n m
F2 n m
FA n m |
JP f,mn
JP NZ,mn
JP Z,mn
JP NC,mn
JP C,mn
JP LZ,mn
JP LO,mn
JP P,mn
JP M,mn |
7 (2,2,2,1)
7 (2,2,2,1)
7 (2,2,2,1)
7 (2,2,2,1)
7 (2,2,2,1)
7 (2,2,2,1)
7 (2,2,2,1)
7 (2,2,2,1)
7 (2,2,2,1) |
if {f} PC = mn
if {NZ} PC = mn
if {Z} PC = mn
if {NC} PC = mn
if {C} PC = mn
if {LZ/NV} PC = mn
if {LO/V} PC = mn
if {P} PC = mn
if {M} PC = mn |
Description
If the condition f is true then the 16-bit data mn is loaded into the Program Counter, PC. If the condition is
false then the Program Counter increments normally.
The condition f is one of the following: NZ, zero flag not set; Z, zero flag set; NC, carry flag not set; C, carry
flag set; LZ, Logical/Overflow flag is not set; LO, Logical/Overflow flag is set; P, sign flag not set; M, sign
flag set.
This instruction recognizes labels when used in the Dynamic C assembler.
|
----
20 e-2
28 e-2
30 e-2
38 e-2 |
JR cc,e
JR NZ,e
JR Z,e
JR NC,e
JR C,e |
5 (2,2,1)
5 (2,2,1)
5 (2,2,1)
5 (2,2,1)
5 (2,2,1) |
if {cc} PC = PC + e
if {NZ} PC = PC + e
if {Z} PC = PC + e
if {NC} PC = PC + e
if {C} PC = PC + e |
Description
If condition cc is true then the 8-bit signed displacement value e is added to the Program Counter, PC.
Since the instruction takes two increments of the PC to complete, two is subtracted from the displacement
value so that the displacement take place from the instruction opcode.
This instruction recognizes labels when used in the Dynamic C assembler.
|
| 18 e-2 |
JR e |
5 (2,2,1) |
PC = PC + e |
Description
Adds a signed constant e to the Program Counter.
Since the instruction takes two increments of the PC to complete, two is subtracted from the displacement
value so that the displacement take place from the instruction opcode.
This instruction recognizes labels when used in the Dynamic C assembler.
|
| CF n m x |
LCALL x,mn |
19 (2,2,2,2,1,3,3,3,1) |
(SP - 1) = PC(low);
(SP - 2) = PC(high);
(SP - 3) = XPC;
XPC = x;
PC = mn;
SP = SP - 3 |
Description
This instruction is similar to the CALL routine in that it transfers program execution to the subroutine address
specified by the 16-bit operand mn. The LCALL instruction is special in that it allows calls to be made to a
computed address in XMEM. Note that the value of XPC and consequently the address space defined by the
XPC is dynamically changed with the LCALL instructions.
In the LCALL instruction, first the Extension of the Program Counter, XPC, is pushed onto the stack. Next
the Program Counter, PC, is pushed onto the stack, the high order byte first, then the low order byte. Then the
XPC is loaded with the 8-bit value x and the PC is loaded with the 16-bit value, mn. The Stack Pointer register
is then updated to reflect the three items pushed onto it.
The value mn must be in the range E000-FFFF.
This instruction is implemented for the Rabbit and is not available for the Z180.
Alternate Forms
The Dynamic C assembler recognizes several other forms of this instruction.
LCALL label
LCALL x,label
LCALL x:label
LCALL x:mn
The parameter label is a user defined label. The colon is equivalent to the comma as a delimiter.
LD (BC),A
LD (DE),A
LD (HL),n
LD (HL),r
|
|
|
| 02 |
LD (BC),A |
7 (2,2,3) |
(BC) = A |
| 12 |
LD (DE),A |
7 (2,2,3) |
(DE) = A |
| 36 n |
LD (HL),n |
7 (2,2,3) |
(HL) = n |
----
77
70
71
72
73
74
75 |
LD (HL),r
LD (HL),A
LD (HL),B
LD (HL),C
LD (HL),D
LD (HL),E
LD (HL),H
LD (HL),L |
6 (2,1,3)
6 (2,1,3)
6 (2,1,3)
6 (2,1,3)
6 (2,1,3)
6 (2,1,3)
6 (2,1,3)
6 (2,1,3) |
(HL) = r
(HL) = A
(HL) = B
(HL) = C
(HL) = D
(HL) = E
(HL) = H
(HL) = L |
Description
-
LD (BC),A: Loads the memory location whose address is the data in word register BC with the data in the Accumulator.
-
LD (DE),A: Loads the memory location whose address is the data in word register DE with the data in the Accumulator.
-
LD (HL),n: Loads the memory location whose address is the data in HL with the 8-bit constant n.
-
LD (HL),r: Loads the memory location whose address is the data in HL, with the data in the register r (any of the registers A, B, C, D, E, H, or L).
|
| DD F4 d |
LD (HL+d),HL |
13 (2,2,2,1,3,3) |
(HL+d) = L; (HL+d+1) = H |
Description
Loads the data in register L into the memory location whose address is the sum of the data in word register
HL and a displacement value d. Then, loads the data in register H into the memory location whose address is
the sum of the data in word register HL and a displacement value d plus 1. This instruction is implemented for
the Rabbit and is not available for the Z180.
LD (IX+d),HL
LD (IX+d),n
LD (IX+d),r
|
|
|
| F4 d |
LD (IX+d),HL |
11 (2,2,1,3,3) |
(IX + d) = L; (IX + d + 1) = H |
| DD 36 d n |
LD (IX+d),n |
11 (2,2,2,2,3) |
(IX + d) = n |
----
DD 77 d
DD 70 d
DD 71 d
DD 72 d
DD 73 d
DD 74 d
DD 75 d |
LD (IX+d),r
LD (IX+d),A
LD (IX+d),B
LD (IX+d),C
LD (IX+d),D
LD (IX+d),E
LD (IX+d),H
LD (IX+d),L |
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3) |
(IX + d) = r
(IX + d) = A
(IX + d) = B
(IX + d) = C
(IX + d) = D
(IX + d) = E
(IX + d) = H
(IX + d) = L |
Description
-
LD (IX+d),HL: Loads the data in register L into the memory location whose address is the sum of the data in index register IX and a displacement value d. Then, loads the data in register H into the memory location whose address is the sum of the data in index register IX and a displacement value d plus 1. This instruction is implemented for the Rabbit and is not available for the Z180.
-
LD (IX+d),n: Loads the 8-bit constant n into the memory location whose address is the sum of index register IX and a displacement value d.
-
LD (IX+d),r: Loads the data in register r (any of the registers A, B, C, D, E, H, or L) into the memory location whose address is the sum of the data in index register IX plus a displacement value d.
LD (IY+d),HL
LD (IY+d),n
LD (IY+d),r
|
|
|
| FD F4 d |
LD (IY+d),HL |
13 (2,2,2,1,3,3) |
(IY + d) = L;
(IY + d + 1) = H |
| FD 36 d n |
LD (IY+d),n |
11 (2,2,2,2,3) |
(IY + d) = n |
----
FD 77 d
FD 70 d
FD 71 d
FD 72 d
FD 73 d
FD 74 d
FD 75 d |
LD (IY+d),r
LD (IY+d),A
LD (IY+d),B
LD (IY+d),C
LD (IY+d),D
LD (IY+d),E
LD (IY+d),H
LD (IY+d),L |
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3)
10 (2,2,2,1,3) |
(IY + d) = r
(IY + d) = A
(IY + d) = B
(IY + d) = C
(IY + d) = D
(IY + d) = E
(IY + d) = H
(IY + d) = L |
Description
-
LD (IY+d),HL: Loads the data in register L into the memory location whose address is the sum of the data in index register IY and a displacement value d. Then, loads the data in register H into the memory location whose address is the sum of the data in index register IY and a displacement value d plus 1. This instruction is implemented for the Rabbit and is not available for the Z180.
-
LD (IY+d),n: Loads the 8-bit constant n into the memory location whose address is the sum of the data in index register IY and a displacement value d.
-
LD (IY+d),r: Loads the data in register r (any of the registers A, B, C, D, E, H, or L) into the memory location whose address is the sum of the data in index register IY plus a displacement value d.
LD (mn),A
LD (mn),HL
LD (mn),IX
LD (mn),IY
LD (mn),ss
|
|
|
| 32 n m |
LD (mn),A |
|
(mn) = A |
| 22 n m |
LD (mn),HL |
|
(mn) = L; (mn + 1) = H |
| DD 22 n m |
LD (mn),IX |
|
(mn) = IX(low); (mn + 1) = IX(high) |
| FD 22 n m |
LD (mn),IY |
|
(mn) = IY(low); (mn + 1) = IY(high) |
----
ED 43 n m
ED 53 n m
ED 63 n m
ED 73 n m |
LD (mn),ss
LD (mn),BC
LD (mn),DE
LD (mn),HL
LD (mn),SP |
|
(mn) = ss(low); (mn + 1) = ss(high)
(mn) = C; (mn + 1) = B
(mn) = E; (mn + 1) = D
(mn) = L; (mn + 1) = H
(mn) = P; (mn + 1) = S |
Clocking: (a)10 (2,2,2,1,3) (b)13 (2,2,2,1,3,3) (c)15 (2,2,2,2,1,3,3) |
Description
-
LD (mn),A: Loads the memory location whose address is mn with the data in the Accumulator.
-
LD (mn),HL: Loads the memory location whose address is mn with the data in register L, then loads the memory location whose address is 1 plus mn with the data in register H.
-
LD (mn),IX: Loads the memory location whose address is mn with the low order byte of the data in index register IX, and the memory location whose address is 1 plus mn with the high order byte of the data in IX.
-
LD (mn),IY: Loads the memory location whose address is mn with the low order byte of the data in index register IY, the memory location whose address is 1 plus mn with the high order byte of the data in IY into.
-
LD (mn),ss: Loads the memory location whose address is mn with the low order byte of the data in word register ss (any of the word registers BC, DE, HL or SP). Then, loads the memory location whose address is 1 plus mn with the high order byte of the data in word register ss.
LD (SP+n),HL
LD (SP+n),IX
LD (SP+n),IY
|
|
|
| D4 n |
LD (SP+n),HL |
11 (2,2,1,3,3) |
(SP + n) = L; (SP + n + 1) = H |
| DD D4 n |
LD (SP+n),IX |
13 (2,2,2,1,3,3) |
(SP + n) = IX(low);
(SP + n + 1) = IX(high) |
| FD D4 n |
LP (SP+n),IY |
13 (2,2,2,1,3,3) |
(SP + n) = IY(low);
(SP + n + 1) = IY(high) |
Description
These instructions are implemented for the Rabbit and are not available for the Z180.
-
LD (SP+n),HL: Loads the data in the register L into the memory location whose address is the sum of the data in the Stack Pointer, SP, and the displacement n. Then loads the data in the register H into the memory location whose address is the sum of the data in SP, the displacement n, and 1.
-
LD (SP+n),IX: Loads the low order byte of the data in index register IX into the memory location whose address is the sum of the data in the Stack Pointer, SP, and the displacement n. Then loads the high order byte of the data in IX into the memory location whose address is the sum of data in SP, the displacement n, and 1.
-
LD (SP+n),IY: Loads the low order byte of the data in index register IY into the memory location whose address is the sum of the data in the Stack Pointer, SP, and the displacement n. Then loads the high order byte of the data in IY into the memory location whose address is the sum of data in SP, the displacement n, and 1.
LD A,(BC)
LD A,(DE)
LD A,(mn)
|
|
|
| 0A |
LD A,(BC) |
6 (2,2,2) |
A = (BC) |
| 1A |
LD A,(DE) |
6 (2,2,2) |
A = (DE) |
| 3A n m |
LD A,(mn) |
9 (2,2,2,1,2) |
A = (mn) |
Description
Loads the Accumulator with the data whose address in memory is:
- the data in word register BC, or
- the data in word register DE, or
- the 16-bit constant mn.
|
| ED 57 |
LD A,EIR |
4 (2,2) |
A = EIR |
| ED 5F |
LD A,IIR |
4 (2,2) |
A = IIR |
Description
-
LD A,EIR: Loads the Accumulator with the data in the External Interrupt Register, EIR. The EIR is used to specify the Most Significant Byte (MSB) of the External Interrupt address. The value loaded in the EIR is concatenated with the appropriate External Interrupt address to form the 16-bit ISR starting address.
-
LD A,IIR: Loads the Accumulator with the data in the Internal Interrupt Register, IIR. The IIR is used to specify the Most Significant Byte (MSB) of the Internal Peripheral Interrupt address. The value loaded in the IIR is concatenated with the appropriate Internal Peripheral address to form the 16-bit ISR starting address for that peripheral.
|
| ED 77 |
LD A,XPC |
4 (2,2) |
A = XPC |
Description
Loads the Accumulator with the data in the Extension of the Program Counter, XPC. This instruction is privileged.
It is implemented for the Rabbit and is not available for the Z180.
|
----
ED 4B n m
ED 5B n m
2A n m
ED 7B n m |
LD dd,(mn)
LD BC,(mn)
LD DE,(mn)
LD HL,(mn)
LD SP,(mn) |
13 (2,2,2,2,1,2,2)
13 (2,2,2,2,1,2,2)
13 (2,2,2,2,1,2,2)
13 (2,2,2,2,1,2,2)
13 (2,2,2,2,1,2,2) |
dd(low) = (mn);
dd(high) = (mn + 1)
C = (mn); B = (mn + 1)
E = (mn); D = (mn + 1)
L = (mn); H = (mn + 1)
SP(low)=(mn); SP(high)=(mn+1) |
Description
Loads the low-order byte of the word register dd (any of the word registers BC, DE, HL or SP) with the data
at memory address mn. Then loads the high-order byte of the word register dd with data at memory address
mn plus 1.
|
----
ED 49
ED 59
ED 69 |
LD dd',BC
LD BC',BC
LD DE',BC
LD HL',BC |
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2) |
dd' = BC
BC' = BC
DE' = BC
HL' = BC |
----
ED 41
ED 51
ED 61 |
LD dd',DE
LD BC',DE
LD DE',DE
LD HL',DE |
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2) |
dd' = DE
BC' = DE
DE' = DE
HL' = DE |
Description
Loads the alternate register pair dd' (any of the registers BC', DE', or HL') with the data in the register pair BC
or the register pair DE. These instructions are implemented for the Rabbit and are not available for the Z180.
|
----
01 n m
11 n m
21 n m
31 n m |
LD dd,mn
LD BC,mn
LD DE,mn
LD HL,mn
LD SP,mn |
6 (2,2,2)
6 (2,2,2)
6 (2,2,2)
6 (2,2,2)
6 (2,2,2) |
dd = mn
BC = mn
DE = mn
HL = mn
SP = mn |
Description
Loads the register pair dd (any of the register pairs BC, DE, HL, or SP) with the 16-bit value mn.
|
| ED 47 |
LD EIR,A |
4 (2,2) |
EIR = A |
| ED 4F |
LD IIR,A |
4 (2,2) |
IIR = A |
Description
-
LD EIR,A: Loads the External Interrupt Register, EIR, with the data in the Accumulator. The EIR is used to specify the Most Significant Byte (MSB) of the External Interrupt address. The value loaded in the EIR is concatenated with the appropriate External Interrupt address to form the 16-bit ISR starting address.
-
LD IIR,A: Loads the Internal Interrupt Register, IIR, with the data in the Accumulator. The IIR is used to specify the Most Significant Byte (MSB) of the Internal Peripheral Interrupt address. The value loaded in the IIR is concatenated with the appropriate Internal Peripheral address to form the 16-bit ISR starting address for that peripheral.
LD HL,(mn)
|
LD HL,(HL+d)
LD HL,(IX+d)
LD HL,(IY+d)
|
|
|
| 2A mn |
LD HL,(mn) |
11 (2,2,2,1,2,2) |
L = (mn); H = (mn + 1) |
| DD E4 d |
LD HL,(HL+d) |
11 (2,2,2,1,2,2) |
L = (HL + d); H = (HL + d + 1) |
| E4 d |
LD HL,(IX+d) |
9 (2,2,1,2,2) |
L = (IX + d); H = (IX + d + 1) |
| FD E4 d |
LD HL,(IY+d) |
11 (2,2,2,1,2,2) |
L = (IY + d); H = (IY + d + 1) |
Description
-
LD HL,(mn): Loads the register L with the data whose address is mn and loads the register H with the data whose address is mn plus 1.
-
LD HL,(HL+d): Loads the register L with the data whose address is the data in word register HL plus a displacement d. Then loads the register H with the data whose address is the data in word register HL plus a displacement d plus 1.
-
LD HL,(IX+d): Loads the register L with the data whose address is the data in index register IX plus a displacement d. Then loads the register H with the data whose address is the data in index register IX plus a displacement d plus 1.
-
LD HL,(IY+d): Loads the register L with the data whose address is the data in index register IY plus a displacement d. Then loads the register H with the data whose address is the data in index register IY plus a displacement d plus 1.
The last 3 instructions are not available for the Z180.
|
| C4 n |
LD HL,(SP+n) |
9 (2,2,1,2,2) |
L = (SP + n); H = (SP + n + 1) |
Description
Loads the register L with the data whose address is the data in index register SP plus a displacement d. Then
loads the register H with the data whose address is the data in index register SP plus a displacement d plus 1.
This instruction is implemented for the Rabbit and is not available for the Z180.
|
| DD 7C |
LD HL,IX |
4 (2,2) |
HL = IX |
| FD 7C |
LD HL,IY |
4 (2,2) |
HL = IY |
Description
These instructions are implemented for the Rabbit and are not available for the Z180.
-
LD HL,IX: Loads the word register HL with the data in index register IX.
-
LD HL,IY: Loads the word register HL with the data in index register IY.
|
| DD 2A n m |
LD IX,(mn) |
|
IX(low) = (mn); IX(high) = (mn + 1) |
*Clocking: 13 (2,2,2,2,1,2,2) |
Description
Loads the low order byte of index register IX with the data whose address is mn. Then loads the high order
byte of IX with the data whose address is mn plus 1.
|
| DD C4 n |
LD IX,(SP+n) |
|
IX(low) = (SP + n); IX(high) = (SP + n + 1) |
*Clocking: 11 (2,2,2,1,2,2) |
Description
Loads the low order byte of index register IX with the data whose address is the data in the Stack Pointer, SP,
plus a displacement n. Then loads the high order byte of IX with the data whose address is the data in the
Stack Pointer register plus a displacement n plus 1. This instruction is implemented for the Rabbit and is not
available for the Z180.
LD IX,HL
LD IX,mn
LD IY,HL
LD IY,mn
|
|
|
| DD 7D |
LD IX,HL |
4 (2,2) |
IX = HL |
| DD 21 n m |
LD IX,mn |
8 (2,2,2,2) |
IX = mn |
| FD 7D |
LD IY,HL |
4 (2,2) |
IY = HL |
| FD 21 n m |
LD IY,mn |
8 (2,2,2,2) |
IY = mn |
Description
-
LD IX,HL: Loads the index register IX with the data in word register HL. This instruction is implemented for the Rabbit and is not available for the Z180
-
LD IX,mn: Loads the index register IX with the 16-bit constant mn.
-
LD IY,HL: Loads the index register IY with the data in word register HL. This instruction is implemented for the Rabbit and is not available for the Z180
-
LD IX,mn: Loads the index register IY with the 16-bit constant mn.
|
| FD 2A n m |
LD IY,(mn) |
|
IY(low) = (mn); IY(high) = (mn + 1) |
*Clocking: 13 (2,2,2,2,1,2,2) |
Description
Loads the low order byte of index register IY with the data at the address mn and loads the high order byte of
IY with the data at the address mn+1.
|
| FD C4 n |
LD IY,(SP+n) |
|
IY(low) = (SP + n); IY(high) = (SP + n + 1) |
*Clocking: 11 (2,2,2,1,2,2) |
Description
Loads the low order byte of index register IY with the data whose address is the data in the Stack Pointer register
SP plus a displacement n. Then loads the high order byte of IY with the data whose address is the data in
the Stack Pointer register plus a displacement n plus 1. This instruction is implemented for the Rabbit and is
not available for the Z180
LD r,(HL)
LD r,(IX+d)
LD r,(IY+d)
|
|
|
----
7E
46
4E
56
5E
66
6E |
LD r,(HL)
LD A,(HL)
LD B,(HL)
LD C,(HL)
LD D,(HL)
LD E,(HL)
LD H,(HL)
LD L,(HL) |
5 (2,1,2)
5 (2,1,2)
5 (2,1,2)
5 (2,1,2)
5 (2,1,2)
5 (2,1,2)
5 (2,1,2)
5 (2,1,2) |
r = (HL)
A = (HL)
B = (HL)
C = (HL)
D = (HL)
E = (HL)
H = (HL)
L = (HL) |
----
DD 7E d
DD 46 d
DD 4E d
DD 56 d
DD 5E d
DD 66 d
DD 6E d |
LD r,(IX+d)
LD A,(IX+d)
LD B,(IX+d)
LD C,(IX+d)
LD D,(IX+d)
LD E,(IX+d)
LD H,(IX+d)
LD L,(IX+d) |
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2) |
r = (IX + d)
A = (IX + d)
B = (IX + d)
C = (IX + d)
D = (IX + d)
E = (IX + d)
H = (IX + d)
L = (IX + d) |
----
FD 7E d
FD 46 d
FD 4E d
FD 56 d
FD 5E d
FD 66 d
FD 6E d |
LD r,(IY+d)
LD A,(IY+d)
LD B,(IY+d)
LD C,(IY+d)
LD D,(IY+d)
LD E,(IY+d)
LD H,(IY+d)
LD L,(IY+d) |
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2)
9 (2,2,2,1,2) |
r = (IY + d)
A = (IY + d)
B = (IY + d)
C = (IY + d)
D = (IY + d)
E = (IY + d)
H = (IY + d)
L = (IY + d) |
Description
Loads the register r (any of the registers A, B, C, D, E, H, or L) with the data whose address is:
- the data in word register HL, or
- the sum of the data in index register IX and a displacement d, or
- the sum of the data in index register IY and a displacement d.
|
----
3E n
06 n
0E n
16 n
1E n
26 n
2E n |
LD r,n
LD A,n
LD B,n
LD C,n
LD D,n
LD E,n
LD H,n
LD L,n |
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2) |
r = n
A = n
B = n
C = n
D = n
E = n
H = n
L = n |
Description
Loads the register r (any of the registers A, B, C, D, E, H, or L) with the 8-bit constant n.
Description
Loads the one-byte register r (any of the registers A, B, C, D, E, H, or L) with the data in another one-byte
register g (any of the registers A, B, C, D, E, H, or L).
|
| F9 |
LD SP,HL |
2 |
SP = HL |
| DD F9 |
LD SP,IX |
4 (2,2) |
SP = IX |
| FD F9 |
LD SP,IY |
4 (2,2) |
SP = IY |
Description
Loads the Stack Pointer register, SP, with the data in (a) the word register HL, (b) the data in index register
IX, or (c) the data in index register IY. These are privileged instructions.
|
| ED 67 |
LD XPC,A |
4 (2,2) |
XPC = A |
Description
Loads the Extension of the Program Counter, XPC, with the data in the Accumulator. This instruction is privileged.
It is implemented for the Rabbit and is not available for the Z180.
|
| ED A8 |
LDD |
10 (2,2,1,2,3) |
(DE) = (HL); BC = BC - 1;
DE = DE - 1; HL = HL - 1 |
| ED B8 |
LDDR |
6 + 7i (2,2,1,(2,3,2)i,1) |
repeat:
(DE) = (HL); BC = BC - 1;
DE = DE - 1; HL = HL - 1
until { BC == 0 } |
| ED A0 |
LDI |
10 (2,2,1,2,3) |
(DE) = (HL); BC = BC - 1;
DE = DE + 1; HL = HL + 1 |
| ED B0 |
LDIR |
6 + 7i (2,2,1,(2,3,2)i,1) |
repeat:
(DE) = (HL); BC = BC - 1;
DE = DE + 1; HL = HL + 1
until { BC == 0 } |
Description
-
LDD: Loads the memory location whose address is in word register DE with the data at the address in word register HL. Then it decrements the data in word registers BC, DE, and HL.
-
LDDR: While the data in the register pair BC does not equal 0 then the memory location whose address is in word register DE is loaded with the data at the address in word register HL. Then it decrements the data in word registers BC, DE, and HL. The instruction then repeats until BC equals zero.
-
LDI: Loads the memory location whose address is in word register DE with the data at the address in word register HL. Then the data in word register BC is decremented and the data in word registers DE and HL is incremented.
-
LDIR: While the data in the register pair BC does not equal 0 then the memory location whose address is in word register DE is loaded with the data at the address in word register HL. Then the data in word register BC is decremented and the data in word registers DE and HL are incremented. The instruction then repeats until BC equals zero.
If any of these block move instructions are prefixed by IOI or IOE, the destination will be in the specified I/O
space. Add 1 clock for each iteration for the prefix if the prefix is IOI (internal I/O). If the prefix is IOE, add 2
clocks plus the number of I/O wait states enabled. The V flag is cleared when BC transitions from 1 to 0. If
the V flag is not cleared another step is performed for the repeating versions of the instructions. Interrupts can
occur between different repeats, but not within an iteration equivalent to LDD or LDI. Return from the interrupt
is to the first byte of the instruction which is the I/O prefix byte if there is one.
