Appendix B. Power Supply

Appendix B provides information on the current requirements of the RCM2300, and some background on the chip select circuit used in power management.

B.1 Power Supplies

The RCM2300 requires a regulated 5 V ± 0.25 V DC power source. The RabbitCore design presumes that the voltage regulator is on the user board, and that the power is made available to the RabbitCore board through headers J4 and J5.

An RCM2300 with no loading at the outputs operating at 22.1 MHz typically draws 108 mA. The RCM2300 will consume an additional 10 mA when the programming cable is used to connect J1 to a PC.

B.2 Battery-Backup Circuits

As explained in Section 2.3.2, the RCM2300 has provision for battery backup, which kicks in to keep VRAM from dropping below 2 V.

The current drain on the battery in a battery-backed circuit must be kept to a minimum. When the RCM2300 is not powered, the battery keeps the SRAM memory contents and the real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces power consumption. This powerdown mode is activated by raising the chip select (CS) signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is required for data retention in powerdown mode. Thus, when power is removed from the circuit, the battery voltage needs to be provided to both the SRAM power pin and to the CS signal line. The CS control switch accomplishes this task for the CS signal line.

Figure B-1 shows a schematic of the chip select control switch.

Figure B-1. Chip Select Control Switch

In a powered-up condition, the CS control switch must allow the processor's chip select signal /CS1 to control the SRAM's CS signal /CSRAM. So, with power applied, /CSRAM must be the same signal as /CS1, and with power removed, /CSRAM must be held high (but only needs to be as high as the battery voltage). Q3 and Q4 are MOSFET transistors with opposing polarity. They are both turned on when power is applied to the circuit. They allow the CS signal to pass from the processor to the SRAM so that the processor can periodically access the SRAM. When power is removed from the circuit, the transistors will turn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 kW pullup resistor to VRAM (R28). This pullup resistor keeps /CSRAM at the VRAM voltage level (which under no power condition is the backup battery's regulated voltage at a little more than 2 V).

Transistors Q3 and Q4 are of opposite polarity so that a rail-to-rail voltages can be passed. When the /CS1 voltage is low, Q3 will conduct. When the /CS1 voltage is high, Q4 will conduct. It takes time for the transistors to turn on, creating a propagation delay. This delay is typically very small, about 10 ns to 15 ns.