Appendix F. External Interrupts

Appendix F provides information about using the RabbitCore RCM2200 external interrupts.

The Rabbit 2000 microprocessor has four external interrupt inputs on Parallel Port E, which is accessed through pins PE0, PE1, PE4, and PE5 on header J4.

Table F-1 lists the general-purpose Parallel Port E I/O pins that can be used for external interrupts.

Table F-1: Rabbit 2000 Parallel Port E Interrupts

Pin	Default Use	Alternate Use
PE0	General- Purpose I/O	INT0A input
PE1		INT1A input
PE4		INT0B input
PE5		INT1B input

Figure F-1 illustrates these pins.

Figure F-1: Rabbit 2000 Interrupt Pins

F.1 Use of External Interrupts

Figure F-2 shows a block diagram of how the Rabbit 2000 external interrupt logic is used in general.

Figure F-2: Rabbit 2000 External Interrupt Logic

Interrupts on the Rabbit 2000 can take place at three priority levels from low to high priority, and are numbered 1, 2 and 3. Each on-chip device, including the two external interrupts, can be assigned a priority at which interrupts will take place. For interrupts that have been assigned the same programmed priority, there is an implicit pri-ority with external interrupt #1 having the highest priority, external interrupt #0 the second highest, and the remaining on-chip devices having lower priorities in the order specified in Section 7.8, "Rabbit Interrupt Structure," in the Rabbit 2000 User's Manual.

The two independent interrupts are generated by inputs to the four pins shown in Figure F-2. Each pin is connected to an edge detector that can be configured under program control to detect rising edges, falling edges, or both. These same pins, a part of parallel port E, support alternate functionality as reflected in Table F-1.

When the edge detector detects the rising or falling edge that it is programmed to detect, it sets a flip-flop that drives the output of the edge detector. The flip-flop should be cleared automatically when the interrupt takes place.

Instead, the flip-flop may be cleared spuriously because a different, lower priority, interrupt occurs nearly simultaneously (during an 8-clock window) with the occurrence of the edge that sets the flip-flop. This results in a lost interrupt.

Or the flip-flop might not be cleared when the interrupt takes place if a different, higher priority, interrupt is being requested nearly simultaneously (during an 8-clock window) with the occurrence of the external interrupt. This results in a spurious interrupt after the first inter-rupt because the interrupt request was not cleared.

In either case, precautions need to be taken if an interrupt request transitions during a short time period 8 clocks long. These sequences are shown schemati-cally in Figure F-3.

Figure F-3: Interrupt Sequences with
Lost or Spurious Interrupts

F.2 Single-Interrupt Request

Tie the inputs for external interrupt #1 and #0 together by adding a 1 kW resistor between the two lines. Under this configuration, shown in Figure F-4, both interrupt #1 and #0 will be requested when an edge is detected. The #1 interrupt will take place first since it is of a higher priority.

Figure F-4: RabbitCore RCM2200 Configuration
for Single-Interrupt Request

The interrupt service routine for interrupt #1 should ignore the interrupt. The actual service routine will be the service routine for interrupt #0. If an interrupt is lost, it will always be #1 and never #0. The 1 kW resistor delays the edge slightly so that interrupt #1 is guaranteed to be latched earlier or simultaneously with interrupt #0. It is important that the programmed priority of interrupt #1 be higher than or equal to the programmed priority of interrupt #0. Normally they should be equal.

Spurious interrupts, which occur because of a failure to clear the request latch, are a possi-bility only if there are other interrupts of higher priority than external interrupt #1 and #0. These can only be the result of programming one of the on-chip peripheral interrupts to have a higher interrupt priority. This could be the case, for example, if the external inter-rupts are programmed to have priority 1, and one of the serial port interrupts is pro-grammed to have priority 2. Spurious interrupts can always be eliminated by programming both external interrupts to have a priority equal to the highest priority used for another device. The priority can be reduced on entry to the service routine to avoid blocking the true high-priority interrupts. External interrupt #1 cannot cause interrupt #0 to have a spurious interrupt or vice versa. In some cases, spurious interrupts may not disturb function, but the fix is so simple that it is not usually worth the trouble to analyze this possibility.

F.3 OR'ed Interrupt Request

Tie the inputs for external interrupt #1 and #0 together by adding a 1 kW resistor. This configuration is shown in Figure F-5.

Figure F-5: RabbitCore RCM2200 Configuration
for OR'ed Interrupt Request