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RLC B
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RLC C
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RLC D
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RLC E
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RLC H
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RLC L
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RLC (HL)
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RLC A
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RRC B
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RRC C
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RRC D
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RRC E
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RRC H
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RRC L
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RRC (HL)
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RRC A
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RL B
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RL C
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RL D
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RL E
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RL H
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RL L
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RL (HL)
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RL A
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RR B
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RR C
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RR D
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RR E
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RR H
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RR L
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RR (HL)
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RR A
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SLA B
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SLA C
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SLA D
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SLA E
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SLA H
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SLA L
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SLA (HL)
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SLA A
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SRA B
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SRA C
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SRA D
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SRA E
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SRA H
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SRA L
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SRA (HL)
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SRA A
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SRL B
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SRL C
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SRL D
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SRL E
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SRL H
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SRL L
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SRL (HL)
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SRL A
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BIT 0,B
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BIT 0,C
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BIT 0,D
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BIT 0,E
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BIT 0,H
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BIT 0,L
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BIT 0, (HL)
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BIT 0,A
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BIT 1,B
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BIT 1,C
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BIT 1,D
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BIT 1,E
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BIT 1,H
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BIT 1,L
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BIT 1, (HL)
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BIT 1,A
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BIT 2,B
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BIT 2,C
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BIT 2,D
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BIT 2,E
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BIT 2,H
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BIT 2,L
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BIT 2, (HL)
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BIT 2,A
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BIT 3,B
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BIT 3,C
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BIT 3,D
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BIT 3,E
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BIT 3,H
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BIT 3,L
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BIT 3,(HL)
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BIT 3,A
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BIT 4,B
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4,C BIT
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BIT 4,D
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BIT 4,E
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BIT 4,H
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BIT 4,L
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BIT 4, (HL)
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BIT 4,A
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BIT 5,B
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BIT 5,C
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BIT 5,D
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BIT 5,E
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BIT 5,H
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BIT 5,L
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BIT 5, (HL)
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BIT 5,A
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BIT 6,B
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BIT 6,C
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BIT 6,D
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BIT 6,E
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BIT 6,H
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BIT 6,L
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BIT 6, (HL)
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BIT 6,A
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BIT 7,B
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BIT 7,C
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BIT 7,D
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BIT 7,E
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BIT 7,H
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BIT 7,L
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BIT 7, (HL)
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BIT 7,A
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RES 0,B
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RES 0,C
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RES 0,D
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RES 0,E
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RES 0,H
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RES 0,L
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RES 0, (HL)
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RES 0,A
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RES 1,B
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RES 1,C
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RES 1,D
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RES 1,E
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RES 1,H
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RES 1,L
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RES 1, (HL)
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RES 1,A
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RES 2,B
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RES 2,C
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RES 2,D
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RES 2,E
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RES 2,H
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RES 2,L
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RES 2, (HL)
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RES 2,A
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RES 3,B
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RES 3,C
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RES 3,D
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RES 3,E
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RES 3,H
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RES 3,L
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RES 3, (HL)
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RES 3,A
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RES 4,B
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RES 4,C
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RES 4,D
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RES 4,E
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RES 4,H
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RES 4,L
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RES 4, (HL)
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RES 4,A
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RES 5,B
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RES 5,C
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RES 5,D
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RES 5,E
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RES 5,H
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RES 5,L
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RES 5, (HL)
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RES 5,A
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RES 6,B
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RES 6,C
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6,D RES
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RES 6,E
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RES 6,H
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RES 6,L
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RES 6, (HL)
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RES 6,A
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RES 7,B
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RES 7,C
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RES 7,D
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RES 7,E
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RES 7,H
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RES 7,L
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RES 7, (HL)
|
RES 7,A
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SET 0,B
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SET 0,C
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SET 0,D
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SET 0,E
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SET 0,H
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SET 0,L
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SET 0, (HL)
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SET 0,A
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SET 1,B
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SET 1,C
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SET 1,D
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SET 1,E
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SET 1,H
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SET 1,L
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SET 1, (HL)
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SET 1,A
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SET 2,B
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SET 2,C
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SET 2,D
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SET 2,E
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SET 2,H
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SET 2,L
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SET 2, (HL)
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SET 2,A
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SET 3,B
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SET 3,C
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SET 3,D
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SET 3,E
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SET 3,H
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SET 3,L
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SET 3, (HL)
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SET 3,A
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SET 4,B
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SET 4,C
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SET 4,D
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SET 4,E
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SET 4,H
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SET 4,L
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SET 4, (HL)
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SET 4,A
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SET 5,B
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SET 5,C
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SET 5,D
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SET 5,E
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SET 5,H
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SET 5,L
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SET 5, (HL)
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SET 5,A
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SET 6,B
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SET 6,C
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SET 6,D
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SET 6,E
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SET 6,H
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SET 6,L
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SET 6, (HL)
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SET 6,A
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SET 7,B
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SET 7,C
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SET 7,D
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SET 7,E
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SET 7,H
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SET 7,L
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SET 7, (HL)
|
SET 7,A
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