IPSET 0
IPSET 1
IPSET 2
IPSET 3     Interrupt Priority Set     Rabbit 2000/3000/4000 Instruction

Opcode	Instruction	Clocks	Operation
ED 46	IPSET 0	4 (2,2)	IP = {IP[5:0], 00}
ED 56	IPSET 1	4 (2,2)	IP = {IP[5:0], 01}
ED 4E	IPSET 2	4 (2,2)	IP = {IP[5:0], 10}
ED 5E	IPSET 3	4 (2,2)	IP = {IP[5:0], 11}

Flags				ALTD			IOI/IOE
S	Z	L/V	C	F	R	SP	S	D
-	-	-	-

Description

IP is an 8-bit register that forms a stack of the current priority and the other previous 3 priorities. IPSET 0 forms the lowest priority; IPSET 3 forms the highest priority.

These are chained-atomic instructions, meaning that an interrupt cannot take place between one of these instructions and the instruction following it.

• IPSET 0: shifts IP 2 bits to the left, then sets bits 0 and 1 of IP to 00
• IPSET 1: shifts IP 2 bits to the left, then sets bits 0 and 1 of IP to 01
• IPSET 2: shifts IP 2 bits to the left, then sets bits 0 and 1 of IP to 10
• IPSET 3: shifts IP 2 bits to the left, then sets bits 0 and 1 of IP to 11

Processor Priority	Effect on Interrupts
0	All interrupts, priority 1,2 and 3, take place after execution of the current non chained-atomic instruction.
1	Only interrupts of priority 2 and 3 take place after execution of the current non chained-atomic instruction.
2	Only interrupts of priority 3 take place after execution of the current non chained-atomic instruction.
3	All interrupts are suppressed. Note that the RST instruction is not an interrupt.