LD rr,(ps+d)
Load
Rabbit 4000 Instruction
|
| -- |
LD rr,(ps+d) |
|
rrlow = (ps+d); rrhigh =(ps+d+1) |
|
6D 00 d
|
LD BC,(PW+d)
|
|
C = (PW+d); B = (PW+d+1)
|
|
6D 10 d
|
LD BC,(PX+d)
|
C = (PX+d); B = (PX+d+1)
|
|
6D 20 d
|
LD BC,(PY+d)
|
C = (PY+d); B = (PY+d+1)
|
|
6D 30 d
|
LD BC,(PZ+d)
|
C = (PZ+d); B = (PZ+d+1)
|
|
6D 40 d
|
LD DE,(PW+d)
|
|
E = (PW+d); D = (PW+d+1)
|
|
6D 50 d
|
LD DE,(PX+d)
|
E = (PX+d); D = (PX+d+1)
|
|
6D 60 d
|
LD DE,(PY+d)
|
E = (PY+d); D = (PY+d+1)
|
|
6D 70 d
|
LD DE,(PZ+d)
|
E = (PZ+d); D = (PZ+d+1)
|
|
6D 80 d
|
LD IX,(PW+d)
|
|
IXlow=(PW+d); IXhigh=(PW+d+1)
|
|
6D 90 d
|
LD IX,(PX+d)
|
IXlow=(PX+d); IXhigh=(PX+d+1)
|
|
6D A0 d
|
LD IX,(PY+d)
|
IXlow=(PY+d); IXhigh=(PY+d+1)
|
|
6D B0 d
|
LD IX,(PZ+d)
|
IXlow=(PZ+d); IXhigh=(PZ+d+1)
|
|
6D C0 d
|
LD IY,(PW+d)
|
|
IYlow=(PW+d); IYhigh=(PW+d+1)
|
|
6D D0 d
|
LD IY,(PX+d)
|
IYlow=(PX+d); IYhigh=(PX+d+1)
|
|
6D E0 d
|
LD IY,(PY+d)
|
IYlow=(PY+d); IYhigh=(PY+d+1)
|
|
6D F0 d
|
LD IY,(PZ+d)
|
IYlow=(PZ+d); IYhigh=(PZ+d+1)
|
Description
Loads rr (any of the 16-bit registers BC, DE, IX or IY) with the data whose address is treated either as a
logical address that will be passed through the MMU for translation into a physical address or as a physical
address that does not need MMU translation. If ps is 0xFFFFxxxx, i.e., the upper 16 bits are all ones, it
represents a logical address. This is called a "long logical" address. Otherwise, it is a physical address with
the low 20 bits or 24 bits being significant (depending on the memory available).
The address is computed as the sum of ps (one of the 32-bit registers PW, PX, PY or PZ) and the 8-bit
signed displacement d.
The instructions "LD IX,(ps+d)" and "LD IY,(ps+d)" are not affected by ALTD.