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Core designs can be developed around the Rabbit 4000 microprocessor. A core design includes memory, the microprocessor, oscillator crystals, the Rabbit 4000 standard programming port, and in some cases, a power controller and power supply. Although modern designs usually use at least four-layer printed circuit boards, two-sided boards are a viable option with the Rabbit 4000, especially if the clock speed is not high and the I/O is intended to operate at 3.3 V--factors that reduce edge speed and electromagnetic radiation.
Schematics illustrating the use of the Rabbit 4000 microprocessor are available online via links in the manuals for the products that are using the Rabbit 4000. Each board-level or core module product has a user manual with an appendix labeled "Schematics." Go to: www.rabbit.com and select "Product Documentation" from the "Support" tab; this will take you to a list of links for available user manuals.
3.1 Clocks
The Rabbit 4000 has input pins for both the fast clock and the 32.768 kHz clock. The fast clock drives the Rabbit 4000 CPU and peripheral clocks, whereas the 32.768 kHz clock is used for the battery-backable clock (also known as the real-time clock), the watchdog timer, the periodic interrupt timer and the asynchronous cold boot function.
The 32.768 kHz oscillator is slow to start oscillating after power-on. For this reason, a wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure. The startup delay may be as much as 5 seconds, but will usually be about 200 ms. Crystals with low series resistance (R < 35 kW) will start faster.
For more information on the 32.768 kHz oscillator please see Technical Note 235, "External 32.768 kHz Oscillator Circuits." This document is available on our website: www.rabbit.com.
3.2 Floating Inputs
Floating inputs or inputs that are not solidly either high or low can draw current because both N and P FETs can turn on at the same time. To avoid excessive power consumption, floating inputs should not be included in a design (except that some inputs may float briefly during power-on sequencing). Most unused inputs on the Rabbit 4000 can be made into outputs by proper software initialization to remove the floating property. Pull-up resistors will be needed on a few inputs that cannot be programmed as outputs. An alternative to a pull-up resistor is to tie an unused output to the unused inputs. If pull-up (or pull-down) resistors are required, they should be made as large as possible if the circuit in question has a substantial part of its duty cycle with current flowing through the resistor.
3.3 Basic Memory Design
Normally /CS0 and /OE0 and /WE0 should be connected to a flash memory that holds the startup code that executes at address zero. When the processor exits reset with (SMODE1, SMODE0) set to (0,0), it will attempt to start executing instructions at the start of the memory connected to /CS0, /OE0, and /WE0.
For Dynamic C to work out of the box, the basic RAM memory must be connected to /CS1, /OE1, and /WE1.
/CS1 has a special property that makes it the preferred chip select for battery-backed RAM. The BIOS defined macro,
CS1_ALWAYS_ON, may be redefined in the BIOS to 1 which will set a bit in the MMIDR register that forces /CS1 to stay enabled (low). This capability can be used to counter a problem encountered when the chip select line is passed through a device that is used to place the chip in standby by raising /CS1 when the power is switched over to battery backup. The battery switchover device typically has a propagation delay that may be 20 ns or more. This is enough to require the insertion of wait states for RAM access in some cases. By forcing /CS1 low, the propagation delay is not a factor because the RAM will always be selected and will be controlled by /OE1 and /WE1. If this is done, the RAM will consume more power while not battery-backed than it would if it were run with dynamic chip select and a wait state. If this special feature is used to speed up access time for battery-backed RAM then no other memory chips should be connected to OE1 and WE1.
Table 3-1 Typical Interface between the Rabbit 4000 and Memory /CS0, /OE0 and /WE0 /CS1, /OE1 and /WE1 /CS2, /OE0 and /WE0 3.3.1 Memory Access Time
Memory access time depends on the clock speed and the capacitive loading of the address and data lines. Wait states can be specified by programming to accommodate slow memories for a given clock speed. Wait states should be avoided with memory that holds programs because there is a significant slowing of the execution speed. Wait states are far more important in the instruction memory than in the data memory since the great majority of accesses are instruction fetches. Going from 0 to 1 wait states is about the same as reducing the clock speed by 30%. Going from 0 to 2 wait states is worth approximately a 45% reduction in clock speed. A table of memory access times required for various clock speeds is given in the Rabbit 4000 Microprocessor User's Manual.
3.3.2 Interfacing External I/O with Rabbit 4000 Designs
The Rabbit 4000 provides on-chip facilities for glueless interfacing to many types of external I/O peripherals. The processor provides a common I/O read and I/O write strobe in addition to eight user configurable I/O strobes that can be used as read, write, read/write, or chip select signals. The Rabbit 4000 also provides the option of enabling a completely separate bus for I/O accesses. The Auxiliary I/O Bus, which uses many of the same pins used by Parallel Port A and the Slave Port, provides 8 data lines and 6 to 8 address lines that are active only during I/O operations. By connecting I/O devices to the auxiliary bus, the fast memory bus is relieved of capacitive loading that would otherwise slow down memory accesses. For core modules based on the Rabbit 4000, fewer pins are required to exit the core module since the slave port and the I/O bus can share the same pins and the memory bus no longer needs to exit the module to provide I/O capability.
As far as external I/O timing is concerned, the Rabbit 4000 provides:
- half a clock cycle of address and chip select hold time for I/O write operations, and
- zero clock cycles of address and chip select hold times for I/O read operations.
These can both be increased to a full clock of hold time. These hold times are true if an I/O device is interfaced to the common memory and I/O bus. However, if an I/O peripheral is interfaced to the Auxiliary I/O bus, address hold time is no longer an issue as the address does not change until the next external I/O operation.
For more information on I/O timing please refer to the Rabbit 4000® Microprocessor User's Manual.
Some I/O peripherals such as LCD controllers and Compact Flash devices require address and chip select hold times for both read and write operations. If the peripheral is interfaced to the Auxiliary I/O bus, address hold time is not an issue. If chip select hold time is required, an unused auxiliary I/O address line can be used to generate the chip select. In situations where I/O peripherals are interfaced to the common memory and I/O bus, address and chip select hold times can be extended under software control or with minor hardware changes. Please refer to Technical Note 227, "Interfacing External I/O with Rabbit 2000/3000 Designs" for additional information. This document is available online at:
www.rabbit.com/docs/app_tech_notes.shtml.3.4 PC Board Layout and Memory Line Permutation
To use the PC board real estate efficiently, it is recommended that the address and data lines to memory be permuted to minimize the use of PC board resources. By permuting the lines, the need to have lines cross over each other on the PC board is reduced, saving feed-through's and space.
For static RAM, address and data lines can be permuted freely, meaning that the address lines from the processor can be connected in any order to the address lines of the RAM, and the same applies for the data lines. For example, if the RAM has 15 address lines and 8 data lines, it makes no difference if A15 from the processor connects to A8 on the RAM and vice versa. Similarly D8 on the processor could connect to D3 on the RAM. The only restriction is that all 8 processor data lines must connect to the 8 RAM data lines. If several different types of RAM can be accommodated in the same PC board footprint, then the upper address lines that are unused if a smaller RAM is installed must be kept in order. For example, if the same footprint can accept either a 128K x 8 RAM with 17 address lines or a 512K x 8 RAM with 19 address lines, then address lines A18 and A19 can be interchanged with each other, but not exchanged with A0-A17.
Permuting lines does make a difference with flash memory and must be avoided in practical systems.
3.5 PC Board Layout and Electromagnetic Interference
Most design failures are related to the layout of the PC board. A good layout results when the effects of electromagnetic interference (EMI) are considered. For detailed information regarding this subject please see Technical Note 221, "PC Board Layout Suggestion for the Rabbit 3000 Microprocessor." This document is available at: www.rabbit.com/docs/app_tech_notes.shtml.
3.5.1 Rabbit 4000 Low EMI Features
The Rabbit 4000 has powerful built-in features to minimize EMI. They are noted here. For details please see The Rabbit 4000 Microprocessor User's Manual.
- Separate power pins exist for core and I/O rings.
- The I/O bus can be separate from the memory bus.
- The external processor bus cycles are not all the same length.
- The external processor bus does not require running the clock around the PCB.
- The clock spectrum spreader option modulates the clock frequency.
- Some gated internal clocks are enabled only when needed.
- An internal clock doubler allows the external crystal oscillator to operate at 1/2 frequency.
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